Seung-Tak Ryu
Orcid: 0000-0002-6947-7785
According to our database1,
Seung-Tak Ryu
authored at least 85 papers
between 2004 and 2023.
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Bibliography
2023
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3<sup>rd</sup>-Order SAR-Assisted CT DSM with 1-0 MASH and DNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 4<sup>th</sup>-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE J. Solid State Circuits, 2022
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration.
IEEE J. Solid State Circuits, 2021
IEEE Access, 2021
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers.
IEEE J. Solid State Circuits, 2019
Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC.
IET Circuits Devices Syst., 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2018
A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme.
IEEE J. Solid State Circuits, 2018
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm<sup>2</sup>.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE J. Solid State Circuits, 2015
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
IEICE Electron. Express, 2015
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs.
IEEE J. Solid State Circuits, 2014
23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE J. Solid State Circuits, 2013
An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution.
IEEE J. Solid State Circuits, 2013
A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2012
A 180-µW, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure.
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development.
IEICE Trans. Electron., 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEICE Trans. Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2007
IEEE J. Solid State Circuits, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2004
IEEE J. Solid State Circuits, 2004