Seung-Tak Ryu

According to our database1, Seung-Tak Ryu authored at least 73 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision.
IEEE Trans. Circuits Syst., 2020

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC.
IEEE Trans. Circuits Syst., 2020

Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron.
IEEE Trans. Circuits Syst., 2020

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability.
IEEE J. Solid State Circuits, 2020

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers.
IEEE J. Solid State Circuits, 2019

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC.
IET Circuits Devices Syst., 2019

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2018

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme.
IEEE J. Solid State Circuits, 2018

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits, 2018

Session 14 overview: High-resolution ADCs: Data converter subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction.
IEEE J. Solid State Circuits, 2017

An incremental zoom sturdy MASH ADC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm<sup>2</sup>.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs.
IEEE J. Solid State Circuits, 2016

F2: Data-converter calibration and dynamic-matching techniques.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation.
IEEE J. Solid State Circuits, 2015

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.
IEEE J. Solid State Circuits, 2015

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC.
IEEE J. Solid State Circuits, 2015

Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs.
IEICE Electron. Express, 2015

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 15 overview: Data-converter techniques: Data converters subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs.
IEEE J. Solid State Circuits, 2014

23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS.
IEEE J. Solid State Circuits, 2013

An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution.
IEEE J. Solid State Circuits, 2013

A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2012

A 180-µW, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure.
IEICE Trans. Electron., 2012

A Single-Supply 84 dB DR Audio-Band ADC for Compact Digital Microphones.
IEICE Trans. Electron., 2012

A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction.
IEEE J. Solid State Circuits, 2011

A 0.014mm<sup>2</sup> 9b switched-current DAC for AMOLED mobile display drivers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A time-domain latch interpolation technique for low power flash ADCs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development.
IEICE Trans. Electron., 2010

A novel readout IC with high noise immunity for charge-based touch screen panels.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones.
IEICE Trans. Electron., 2009

A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse.
IEEE J. Solid State Circuits, 2007

2006
A 10b 50MS/s pipelined ADC with opamp current reuse.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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