Rezaul Haque

According to our database, Rezaul Haque authored at least 6 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

On-chip charge pump design for 3D non-volatile flash memory: from industry perspective.

Rezaul Haque, Siraj Fulum Mossa

Integr., January, 2024

2023

Data-Driven Solution to Identify Sentiments from Online Drug Reviews.

Rezaul Haque, Saddam Hossain Laskar, Katura Gania Khushbu, Md Junayed Hasan, Jia Uddin

Comput., April, 2023

A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density.

Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, Chang-Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen Prabhu V, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie-Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, Bharat Pathak, Pranav Kalavade

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm² Bit Density.

Ali Khakifirooz, Sriram Balasubrahmanyam, Richard Fastow, Kristopher H. Gaewsky, Chang-Wan Ha, Rezaul Haque, Owen Jungroth, Steven Law, Aliasgar S. Madraswala, Binh Ngo, Naveen Prabhu V, Shantanu Rajwade, Karthikeyan Ramamurthi, Rohit S. Shenoy, Jacqueline Snyder, Cindy Sun, Deepak Thimmegowda, Bharat Pathak, Pranav Kalavade

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2007

Design of a flash-based reference voltage generator for drain bias circuit.

Rezaul Haque, Kerry Tedrow, Balaji Srinivasan

IET Circuits Devices Syst., 2007

2006

Design of a high-speed, low-noise CMOS data output buffer.

Rezaul Haque, Andrzej Sendrowski, Bob Baltar, Saad Monasa

Integr., 2006