According to our database1, Woopyo Jeong authored at least 16 papers between 2002 and 2020.
Legend:Book In proceedings Article PhD thesis Other
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.
IEEE J. Solid State Circuits, 2012
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010
IEICE Trans. Electron., 2007
Low-power carry-select adder using adaptive supply voltage based on input vector patterns.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002