Sunghwa Ok
According to our database1,
Sunghwa Ok
authored at least 7 papers
between 2007 and 2021.
Collaborative distances:
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Bibliography
2021
A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm<sup>2</sup> Density with a Peripheral Circuit Under Cell Array Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2012
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2010
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
2008
A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007