Riadh Ben Abdelhamid

According to our database, Riadh Ben Abdelhamid authored at least 14 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card.

Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

BRISKI: A RISC-V barrel processor approach for higher throughput with less resource tax.

Riadh Ben Abdelhamid, Dirk Koch

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture.

Yuxi Tan, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Masaru Nishimura, Yoshiki Yamaguchi

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance.

Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Yoshiki Yamaguchi

Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024

MPD - Multi-Project Die Sharing Enabled by an Embedded FPGA.

Dirk Koch, Myrtle Shah, Gavaskar Kanagara, Riadh Ben Abdelhamid, Nguyen Dao

Proceedings of the International Conference on Field Programmable Technology, 2024

SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay.

Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Quantitative study of floating-point precision on modern FPGAs.

Riadh Ben Abdelhamid, Gen Kuwazawa, Yoshiki Yamaguchi

Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2022

Packed SIMD Vectorization of the DRAGON2-CB.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2021

A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

IEEE Access, 2021

2020

Condensing an overload of parallel computing ingredients into a single architecture recipe.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

MITRACA: A Next-Gen Heterogeneous Architecture.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture.

Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019