Vladislav Válek

According to our database, Vladislav Válek authored at least 5 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs.

Vladislav Válek, Martin Spinler, Jakub Cabal, Tomás Martínek

Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems.

Riadh Ben Abdelhamid, Vladislav Válek, Kevin Klein, Dirk Koch

Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

2024

SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card.

Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay.

Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs.

Jakub Cabal, Vladislav Válek, Martin Spinler, Daniel Kondys, Jan Korenek

Proceedings of the IEEE INFOCOM 2023, 2023