Riadul Islam

Orcid: 0000-0002-4649-3467

According to our database1, Riadul Islam authored at least 25 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks.
Sensors, February, 2024

2023
Design Automation of Series Resonance Clocking in 14-nm FinFETs.
Circuits Syst. Signal Process., December, 2023

Introduction to Medical Imaging Informatics.
CoRR, 2023

Deep Image Segmentation for Defect Detection in Photo-lithography Fabrication.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Resonant Compute-In-Memory (rCIM) 10T SRAM Macro for Boolean Logic.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
GGNB: Graph-based Gaussian naive Bayes intrusion detection system for CAN bus.
Veh. Commun., 2022

Graph-Based Intrusion Detection System for Controller Area Networks.
IEEE Trans. Intell. Transp. Syst., 2022

Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Negative Capacitance Clock Distribution.
IEEE Trans. Emerg. Top. Comput., 2021

Resonant Energy Recycling SRAM Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design and Implementation of Efficient Electric Vehicle with Clean Energy.
Proceedings of the International Conference on Information Technology, 2021

2019
HCDN: Hybrid-Mode Clock Distribution Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Soft Voting-Based Ensemble Approach to Predict Early Stage DRC Violations.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Predicting DRC Violations Using Ensemble Random Forest Algorithm.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops.
J. Electron. Test., 2018

2017
CMCS: Current-Mode Clock Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Differential current-mode clock distribution.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

LC resonant clock resource minimization using compensation capacitance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Switched capacitor quasi-adiabatic clocks.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Current-mode clock distribution.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012
A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A high performance clock precharge SEU hardened flip-flop.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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