Ricardo Santos

Orcid: 0000-0002-2955-8011

Affiliations:
  • Federal University of Mato Grosso do Sul, Campo Grande, MS, Brazil
  • Dom Bosco Catholic University, Campo Grande, MS, USA (former)
  • State University of Campinas, SP, Brazil (former)


According to our database1, Ricardo Santos authored at least 21 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Performance predictors for graphics processing units applied to dark-silicon-aware design space exploration.
Concurr. Comput. Pract. Exp., 2023

Software Testing applied to the Development of IoT Systems: preliminary results.
Proceedings of the 8th Brazilian Symposium on Systematic and Automated Software Testing, 2023

2020
A Physiological-Monitoring Electronic Platform for Cattle Grazing Systems.
Int. J. Agric. Environ. Inf. Syst., 2020

Ingestive Behaviour Activities Based on Bioacoustic Signals in Grazing Cattle.
Int. J. Agric. Environ. Inf. Syst., 2020

2019
Performance Models for Heterogeneous Systems Applied to the Dark Silicon-Aware Design Space Exploration.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

2018
Dark-Silicon Aware Design Space Exploration.
J. Parallel Distributed Comput., 2018

2016
Instruction set independent program encoding.
Des. Autom. Embed. Syst., 2016

On the Dark Silicon Automatic Evaluation on Multicore Processors.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Thread Footprint Analysis for the Design of Multithreaded Applications and Multicore Systems.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

2015
Instruction decoders based on pattern factorization.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

MultiExplorer: A tool set for multicore system-on-chip design exploration.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
A framework for instruction encoding designs on embedded processors.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

2012
Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor.
Proceedings of the 13th Symposium on Computer Systems, 2012

2009
A pattern based instruction encoding technique for high performance architectures.
Int. J. High Perform. Syst. Archit., 2009

Multiple Valued Logic Algebra for the Synthesis of Digital Circuits.
Proceedings of the ISMVL 2009, 2009

2008
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor.
J. Univers. Comput. Sci., 2008

2007
2D-VLIW: a processor architecture based on the geometry of the computation.
PhD thesis, 2007

2006
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2D-VLIW: An Architecture Based on the Geometry of Computation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2004
A New Implementation for Parallel Processing Based on CORBA Standard.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004


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