Guido Araujo
Orcid: 0000-0003-4869-5190Affiliations:
- University of Campinas (UNICAMP), Institute of Computing, Sao Paulo, Brazil
According to our database1,
Guido Araujo
authored at least 132 papers
between 1994 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Computers, January, 2024
2023
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions.
ACM Trans. Archit. Code Optim., December, 2023
Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering.
Softw. Pract. Exp., September, 2023
ACM Trans. Archit. Code Optim., June, 2023
MassCCS: A High-Performance Collision Cross-Section Software for Large Macromolecular Assemblies.
J. Chem. Inf. Model., June, 2023
J. Parallel Distributed Comput., May, 2023
J. Parallel Distributed Comput., March, 2023
2022
ACM Trans. Archit. Code Optim., 2022
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops, 2022
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops, 2022
Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
ACM Trans. Archit. Code Optim., 2021
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021
Pooling Acceleration in the DaVinci Architecture Using Im2col and Col2im Instructions.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Euro-Par 2021: Parallel Processing, 2021
2020
Proceedings of the Companion of the 2020 ACM/SPEC International Conference on Performance Engineering, 2020
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020
Proceedings of the OpenMP: Portable Multi-Level Parallelism on Modern Systems, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
Proceedings of the Euro-Par 2020: Parallel Processing, 2020
2019
IEEE Trans. Parallel Distributed Syst., 2019
Data-flow analysis and optimization for data coherence in heterogeneous architectures.
J. Parallel Distributed Comput., 2019
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
IEEE Trans. Parallel Distributed Syst., 2018
ACM Trans. Archit. Code Optim., 2018
Microprocess. Microsystems, 2018
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
ACM Trans. Archit. Code Optim., 2017
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017
Proceedings of the Scaling OpenMP for Exascale Performance and Portability, 2017
Proceedings of the International Conference on Supercomputing, 2017
Proceedings of the 46th International Conference on Parallel Processing, 2017
Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories.
Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017
2016
Study of hardware transactional memory characteristics and serialization policies on Haswell.
Parallel Comput., 2016
Proceedings of the String Processing and Information Retrieval, 2016
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016
Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Proceedings of the 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, 2015
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015
Performance implications of dynamic memory allocators on transactional memory systems.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
Int. J. Parallel Program., 2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Proceedings of the Using and Improving OpenMP for Devices, Tasks, and More, 2014
Proceedings of the 43rd International Conference on Parallel Processing, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Softw. Pract. Exp., 2013
Int. J. Parallel Program., 2013
Proceedings of the IEEE International Symposium on Workload Characterization, 2013
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
2012
Data center power and performance optimization through global selection of P-states and utilization rates.
Sustain. Comput. Informatics Syst., 2012
Des. Autom. Embed. Syst., 2012
Proceedings of the 13th Symposium on Computer Systems, 2012
2011
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011
2010
Proceedings of the Computer Architecture, 2010
Proceedings of the Computer Architecture, 2010
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010
T-DRE: a hardware trusted computing base for direct recording electronic vote machines.
Proceedings of the Twenty-Sixth Annual Computer Security Applications Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Comput. Archit. Lett., 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
2008
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor.
J. Univers. Comput. Sci., 2008
2007
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F<sub>2<sup>163</sup></sub> using Gaussian Normal Bases.
J. VLSI Signal Process., 2007
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
2006
ACM Trans. Embed. Comput. Syst., 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation.
ACM J. Exp. Algorithmics, 2005
Int. J. Parallel Program., 2005
Platform designer: An approach for modeling multiprocessor platforms based on SystemC.
Des. Autom. Embed. Syst., 2005
Des. Autom. Embed. Syst., 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
A custom instruction approach for hardware and software implementations of finite field arithmetic over F<sub>2<sup>63</sup></sub> using Gaussian normal bases.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
Proceedings of the Forum on specification and Design Languages, 2005
2004
ACM Trans. Embed. Comput. Syst., 2004
The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation.
Proceedings of the Experimental and Efficient Algorithms, Third International Workshop, 2004
Proceedings of the 2004 workshop on Computer architecture education, 2004
An automatic testbench generation tool for a SystemC functional verification methodology.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Microelectron. J., 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the Compiler Construction, 10th International Conference, 2001
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
Proceedings of the 2001 International Conference on Compilers, 2001
2000
Expression-tree-based algorithms for code compression on embedded RISC architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Proceedings of the Languages, 2000
1999
Proceedings of the 12th International Symposium on System Synthesis, 1999
1998
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998
1996
Instruction Set Design and Optimizations for Address Computation in DSP Architectures.
Proceedings of the 9th International Symposium on System Synthesis, 1996
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.
Proceedings of the 33st Conference on Design Automation, 1996
1995
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
1994
Challenges in code generation for embedded processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994