Rodolfo Azevedo

Orcid: 0000-0002-8803-0401

Affiliations:
  • University of Campinas, São Paulo, Brazil


According to our database1, Rodolfo Azevedo authored at least 87 papers between 2000 and 2023.

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Bibliography

2023
Perceptual Learning Modules (PLM) in CS1: a Negative Result and a Methodological Warning.
J. Univers. Comput. Sci., September, 2023

Usabilidade dos Ambientes Virtuais de Aprendizagem Canvas e Blackboard: Caso de estudo em uma Universidade Brasileira.
Revista Brasileira de Informática na Educ., 2023

When Test Cases Are Not Enough: Identification, Assessment, and Rationale of Misconceptions in Correct Code (MC³).
Revista Brasileira de Informática na Educ., 2023

A Syllabi Analysis of CS1 Courses from Brazilian Public Universities.
Revista Brasileira de Informática na Educ., 2023

DONUTS: An efficient method for checkpointing in non-volatile memories.
Concurr. Comput. Pract. Exp., 2023

Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

2022
Optically connected memory for disaggregated data centers.
J. Parallel Distributed Comput., 2022

Prof5: A RISC-V profiler tool.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

How much C can students learn in one week? Experiences teaching C in advanced CS courses.
Proceedings of the IEEE Frontiers in Education Conference, 2022

A Computational Thinking Course for Pre-Service Teachers.
Proceedings of the IEEE Global Engineering Education Conference, 2022

2020
Application-Oriented Retinal Image Models for Computer Vision.
Sensors, 2020

AxRAM: A lightweight implicit interface for approximate data access.
Future Gener. Comput. Syst., 2020

ADeLe: A description language for approximate hardware.
Future Gener. Comput. Syst., 2020

Bringing Energy Information to the Instruction Set.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

A SystemC profiling framework to improve fixed-point hardware utilization.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Optically Connected Memory for Disaggregated Data Centers.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

2019
AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction.
ACM Trans. Archit. Code Optim., 2019

A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems.
IEEE Embed. Syst. Lett., 2019

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.
CoRR, 2019

A Resilient Interface for Approximate Data Access.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-Precision Computing.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

Identifying and Validating Java Misconceptions Toward a CS1 Concept Inventory.
Proceedings of the 2019 ACM Conference on Innovation and Technology in Computer Science Education, 2019

2018
Dark-Silicon Aware Design Space Exploration.
J. Parallel Distributed Comput., 2018

Phase Detection and Analysis among Multiple Program Inputs.
Proceedings of the Symposium on High Performance Computing Systems, 2018

A Methodology for Optimization of Interpreters.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Impact of Memory Approximation on Energy Efficiency.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Exploring Active Learning Approaches to Computer Science Classes.
Proceedings of the 49th ACM Technical Symposium on Computer Science Education, 2018

ADeLe: Rapid Architectural Simulation for Approximate Hardware.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Optically connected and reconfigurable GPU architecture for optimized peer-to-peer access.
Proceedings of the International Symposium on Memory Systems, 2018

2017
HybridVerifier: A Cross-Platform Verification Framework for Instruction Set Simulators.
IEEE Embed. Syst. Lett., 2017

Exploiting performance, dynamic power and energy scaling in full-system simulators.
Concurr. Comput. Pract. Exp., 2017

A socially inspired energy feedback technology: challenges in a developing scenario.
AI Soc., 2017

2016
Design and evaluation of compact ISA extensions.
Microprocess. Microsystems, 2016

MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies.
J. Parallel Distributed Comput., 2016

Developing a Computer Science Concept Inventory for Introductory Programming.
Proceedings of the 47th ACM Technical Symposium on Computing Science Education, 2016

On the Dark Silicon Automatic Evaluation on Multicore Processors.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Scalability evaluation in many-core systems due to the memory organization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Architecting a computer with a full optical RAM.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Temporal frequent value locality.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
SHRINK: reducing the ISA complexity via instruction recycling.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

MultiExplorer: A tool set for multicore system-on-chip design exploration.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Cloud-based OpenMP Parallelization Using a MapReduce Runtime.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

MPSoCBench: A toolset for MPSoC system level evaluation.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Wear-out analysis of Error Correction Techniques in Phase-Change Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An automatic energy consumption characterization of processors using ArchC.
J. Syst. Archit., 2013

Zombie memory: extending memory lifetime by reviving dead blocks.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Data center power and performance optimization through global selection of P-states and utilization rates.
Sustain. Comput. Informatics Syst., 2012

A transactional runtime system for the Cell/BE architecture.
J. Parallel Distributed Comput., 2012

Optimizing Simulation in Multiprocessor Platforms Using Dynamic-Compiled Simulation.
Proceedings of the 13th Symposium on Computer Systems, 2012

Energy-Performance Tradeoffs in Software Transactional Memory.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

An ArchC approach for automatic energy consumption characterization of processors.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

2011
Ferramenta de apoio para o aprendizado ativo usando dispositivos com caneta eletrônica.
Revista Brasileira de Informática na Educ., 2011

Using multiple abstraction levels to speedup an MPSoC virtual platform simulator.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Empirical Web server power modeling and characterization.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

2010
STM versus lock-based systems: an energy consumption perspective.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A pattern based instruction encoding technique for high performance architectures.
Int. J. High Perform. Syst. Archit., 2009

Characterizing the Energy Consumption of Software Transactional Memory.
IEEE Comput. Archit. Lett., 2009

On the energy-efficiency of software transactional memory.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

SPARC16: A New Compression Approach for the SPARC Architecture.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2008
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor.
J. Univers. Comput. Sci., 2008

A Software Transactional Memory System for an Asymmetric Processor Architecture.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

On the Limitations of Power Macromodeling Techniques.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A multi-model power estimation engine for accuracy optimization.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2D-VLIW: An Architecture Based on the Geometry of Computation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
The ArchC Architecture Description Language and Tools.
Int. J. Parallel Program., 2005

Platform designer: An approach for modeling multiprocessor platforms based on SystemC.
Des. Autom. Embed. Syst., 2005

A SystemC-only design methodology and the CINE-IP multimedia platform.
Des. Autom. Embed. Syst., 2005

Design of a decompressor engine on a SPARC processor.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Exploiting the Area X Performance Trade-off with Code Compression.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

High-Level Switching Activity Prediction Through Sampled Monitored Simulation.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Processor Centric Specification and Modelling of MPSoCs.
Proceedings of the Forum on specification and Design Languages, 2005

2004
Teaching computer architecture using an architecture description language.
Proceedings of the 2004 workshop on Computer architecture education, 2004

ArchC: A SystemC-Based Architecture Description Language.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Multi-Profile Instruction Based Compression.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Optimizations for Compiled Simulation Using Instruction Type Information.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Fast instruction set custornization.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.
Proceedings of the 2004 Design, 2004

Multi-profile based code compression.
Proceedings of the 41th Design Automation Conference, 2004

2003
Exploring Memory Hierarchy with ArchC.
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

Mixed static/dynamic profiling for dictionary based code compression.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Uma arquitetura para execução de codigo comprimido em sistemas dedicados.
PhD thesis, 2002

2001
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Expression-tree-based algorithms for code compression on embedded RISC architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2000


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