Richard M. Chou

According to our database, Richard M. Chou authored at least 5 papers between 1994 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Testable Sequential Circuit Design: A Partition and Resynthesis Approach.

Richard M. Chou, Kewal K. Saluja

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

1997

Scheduling tests for VLSI systems under power constraints.

Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal

IEEE Trans. Very Large Scale Integr. Syst., 1997

Sequential Circuit Testing: From DFT to SFT.

Richard M. Chou, Kewal K. Saluja

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995

Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan.

Ning Jiang, Richard M. Chou, Kewal K. Saluja

Proceedings of the Digest of Papers: FTCS-25, 1995

1994

Power Constraint Scheduling of Tests.

Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal

Proceedings of the Seventh International Conference on VLSI Design, 1994