Ritaro Takenaka

According to our database, Ritaro Takenaka authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators.

Ritaro Takenaka, Tetsuya Iizuka

IEEE J. Solid State Circuits, April, 2026

A 91.8-dB SNDR 24-kHz BW Discrete-Time ΔΣ ADC Employing Gain-Switched FIA With Sampling Noise Cancellation.

Ximing Wang, Yuyang Zhu, Haoming Zhang, Yunjie Chen, Jiaao Yu, Sota Kano, Ritaro Takenaka, Shuowei Li, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka

IEEE Trans. Circuits Syst. II Express Briefs, January, 2026

A 10-bit 20-GS/s 4-Channel Time-Interleaved DAC Employing Hybrid-Segmentation in 28-nm CMOS.

Yunjie Chen, Ckristian Duran, Koji Asami, Sota Kano, Ritaro Takenaka, Zolboo Byambadorj, Masahiro Ishida, Akio Higo, Tetsuya Iizuka

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework.

Shuowei Li, Ckristian Duran, Ritaro Takenaka, Tetsuya Iizuka

IEEE Access, 2025