Sota Kano

According to our database, Sota Kano authored at least 4 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 91.8-dB SNDR 24-kHz BW Discrete-Time ΔΣ ADC Employing Gain-Switched FIA With Sampling Noise Cancellation.

Ximing Wang, Yuyang Zhu, Haoming Zhang, Yunjie Chen, Jiaao Yu, Sota Kano, Ritaro Takenaka, Shuowei Li, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka

IEEE Trans. Circuits Syst. II Express Briefs, January, 2026

A 10-bit 20-GS/s 4-Channel Time-Interleaved DAC Employing Hybrid-Segmentation in 28-nm CMOS.

Yunjie Chen, Ckristian Duran, Koji Asami, Sota Kano, Ritaro Takenaka, Zolboo Byambadorj, Masahiro Ishida, Akio Higo, Tetsuya Iizuka

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes.

Sota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

150GHz Fundamental Oscillator Utilizing Transmission-Line-Based Inter-Stage Matching in 130nm SiGe BiCMOS Technology.

Sota Kano, Tetsuya Iizuka

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024