Robert F. Molyneaux

According to our database, Robert F. Molyneaux authored at least 9 papers between 1989 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip.

Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh

Proceedings of the 2007 IEEE International Test Conference, 2007

2003

Debug and Diagnosis in the Age of System-on-a-Chip.

Robert F. Molyneaux

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2000

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.

Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

DFT advances in Motorola's Next-Generation 74xx PowerPC^TM microprocessor.

Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.

Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.

Rajesh Raina, Robert F. Molyneaux

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

How Seriously Do You Take Your Possible-Detect Faults?

Rajesh Raina, Charles Njinda, Robert F. Molyneaux

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Efficient Testing of Clock Regenerator Circuits in Scan Designs.

Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh

Proceedings of the 34st Conference on Design Automation, 1997

1989

Comments on "Ternary Scan Design for VLSI Testability".

Robert F. Molyneaux, Alexander Albicki

IEEE Trans. Computers, 1989