Nandu Tendolkar

According to our database, Nandu Tendolkar authored at least 6 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.

Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture.

Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2002

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.

Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.

Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.

Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999