Charles Njinda

According to our database, Charles Njinda authored at least 12 papers between 1991 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2004

A Hierarchical DFT Architecture for Chip, Board and System Test/Debug.

Charles Njinda

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

1997

How Seriously Do You Take Your Possible-Detect Faults?

Rajesh Raina, Charles Njinda, Robert F. Molyneaux

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Efficient Testing of Clock Regenerator Circuits in Scan Designs.

Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh

Proceedings of the 34st Conference on Design Automation, 1997

1995

Performance Driven BIST Technique for Random Logic.

Charles Njinda, Neeraj Kaul

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

SWiTEST: a switch level test generation system for CMOS combinational circuits.

Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.

Ishwar Parulkar, Melvin A. Breuer, Charles Njinda

Proceedings of the 31st Conference on Design Automation, 1994

1993

Generating a family of testable designs using the BILBO methodology.

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer

J. Electron. Test., 1993

1992

Optimal Sequencing of Scan Registers.

Sridhar Narayanan, Charles Njinda, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

SIESTA: a multi-facet scan design system.

Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer

Proceedings of the conference on European design automation, 1992

1991

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing.

Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.

Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Systematic Approach for Designing Testable VLSI Circuits.

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991