Robert J. Stewart

Orcid: 0000-0003-0365-693X

Affiliations:
  • Heriot Watt University, Edinburgh, Department of Computer Science


According to our database1, Robert J. Stewart authored at least 40 papers between 1984 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis.
J. Signal Process. Syst., October, 2023

Introducing and Interfacing with Cybersecurity - A Cards Approach.
CoRR, 2023

Logic of Differentiable Logics: Towards a Uniform Semantics of DL.
Proceedings of the LPAR 2023: Proceedings of 24th International Conference on Logic for Programming, 2023

2022
Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2022

Why functional program synthesis matters (in the realm of genetic programming).
Proceedings of the GECCO '22: Genetic and Evolutionary Computation Conference, Companion Volume, Boston, Massachusetts, USA, July 9, 2022

Benchmarking Parallelism in Unikernels.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip.
Proceedings of the IEEE Intl. Conf. on Dependable, 2022

Differentiable Logics for Neural Network Training and Verification.
Proceedings of the Software Verification and Formal Methods for ML-Enabled Autonomous Systems, 2022

2021
Property-driven Training: All You (N)Ever Wanted to Know About.
CoRR, 2021

2020
YewPar: skeletons for exact combinatorial search.
Proceedings of the PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020

Relative Robustness of Quantized Neural Networks Against Adversarial Attacks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Verifying parallel dataflow transformations with model checking and its application to FPGAs.
J. Syst. Archit., 2019

Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing.
J. Imaging, 2019

Neural Network Verification for the Masses (of AI graduates).
CoRR, 2019

Graphical program transformations for embedded systems.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Implementing YewPar: A Framework for Parallel Tree Search.
Proceedings of the Euro-Par 2019: Parallel Processing, 2019

2018
RIPL: A Parallel Image Processing Language for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Replicable parallel branch and bound search.
J. Parallel Distributed Comput., 2018

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Parallel Mean Shift Accuracy and Performance Trade-Offs.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Profile Guided Dataflow Transformation for FPGAs and CPUs.
J. Signal Process. Syst., 2017

Towards Generic Scalable Parallel Combinatorial Search.
Proceedings of the International Workshop on Parallel Symbolic Computation, 2017

Recursive Array Comprehensions in a Call-by-Value Language.
Proceedings of the 29th Symposium on Implementation and Application of Functional Programming Languages, 2017

Power efficient dataflow design for a heterogeneous smart camera architecture.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Transparent fault tolerance for scalable functional computation.
J. Funct. Program., 2016

A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

An Image Processing Language: External and Shallow/Deep Embeddings.
Proceedings of the 1st International Workshop on Real World Domain Specific Languages, 2016

2015
RIPL: An Efficient Image Processing DSL for FPGAs.
CoRR, 2015

2014
Reliable scalable symbolic computation: The design of SymGridPar2.
Comput. Lang. Syst. Struct., 2014

The HdpH DSLs for scalable reliable computation.
Proceedings of the 2014 ACM SIGPLAN symposium on Haskell, 2014

Profile driven dataflow optimisation of mean shift visual tracking.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

A Demonstration of a Natural Language Query Interface to an Event-Based Semantic Web Triplestore.
Proceedings of the Semantic Web: ESWC 2014 Satellite Events, 2014

2013
Reliable massively parallel symbolic computing: fault tolerance for a distributed Haskell.
PhD thesis, 2013

Demonstrating SerenA: Chance Encounters in the Space of Ideas.
Proceedings of the Advances on Practical Applications of Agents and Multi-Agent Systems, 2013

SerenA: A Multi-site Pervasive Agent Environment That Supports Serendipitous Discovery in Research.
Proceedings of the Advances on Practical Applications of Agents and Multi-Agent Systems, 2013

2012
Supervised Workpools for Reliable Massively Parallel Computing.
Proceedings of the Trends in Functional Programming - 13th International Symposium, 2012

2011
Comparing High Level MapReduce Query Languages.
Proceedings of the Advanced Parallel Processing Technologies - 9th International Symposium, 2011

1984
Customer control of network services.
IEEE Commun. Mag., 1984


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