Rongchun Li

Orcid: 0000-0001-5922-7961

According to our database1, Rongchun Li authored at least 43 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
High performance dilated convolutions on multi-core DSPs.
CCF Trans. High Perform. Comput., February, 2024

2022
Hierarchical learning with backtracking algorithm based on the Visual Confusion Label Tree for large-scale image classification.
Vis. Comput., 2022

A pipelining strategy for accelerating convolution neural networks on ARM CPUs.
Concurr. Comput. Pract. Exp., 2022

MLPs: Efficient Training of MiniGo on Large-scale Heterogeneous Computing System.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

2021
Ddper: Decentralized Distributed Prioritized Experience Replay.
Proceedings of the 2021 IEEE International Conference on Multimedia and Expo, 2021

2020
DropFilterR: A Novel Regularization Method for Learning Convolutional Neural Networks.
Neural Process. Lett., 2020

Annealed gradient descent for deep learning.
Neurocomputing, 2020

Fixed-size Objects Encoding for Visual Relationship Detection.
CoRR, 2020

A High-Throughput LDPC Decoder Based on GPUs for 5G New Radio.
Proceedings of the IEEE Symposium on Computers and Communications, 2020

Towards Precise End-to-end Semi-Supervised Human Head Detection Network.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

End-to-end Spatial Attention Network with Feature Mimicking for Head Detection.
Proceedings of the 15th IEEE International Conference on Automatic Face and Gesture Recognition, 2020

2019
GBCNN: A Full GPU-Based Batch Multi-Task Cascaded Convolutional Networks.
IEEE Access, 2019

A Pipelining Strategy for Accelerating Convolutional Networks on ARM Processors.
Proceedings of the Parallel Architectures, Algorithms and Programming, 2019

An Efficient Parallel Successive Cancellation List Polar Decoder Based on GPUs.
Proceedings of the 2019 IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2019

Accelerated Inference Framework of Sparse Neural Network Based on Nested Bitmask Structure.
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019

Fast Nonlocal Diffusion by Stacking Local Filters for Image Denoising.
Proceedings of the Data Science, 2019

A Parallel Turbo Product Codes Decoder Based on Graphics Processing Units.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
An efficient CPU-GPU hybrid parallel implementation for DVB-RCS2 receiver.
Concurr. Comput. Pract. Exp., 2018

Spatial Attention Network for Head Detection.
Proceedings of the Advances in Multimedia Information Processing - PCM 2018, 2018

Visual Confusion Label Tree for Image Classification.
Proceedings of the 2018 IEEE International Conference on Multimedia and Expo, 2018

Temporal Pyramid Relation Network for Video-Based Gesture Recognition.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Deep Image Clustering Using Convolutional Autoencoder Embedding with Inception-Like Block.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017
Ranking Support Vector Machine with Kernel Approximation.
Comput. Intell. Neurosci., 2017

Learning Non-local Image Diffusion for Image Denoising.
Proceedings of the 2017 ACM on Multimedia Conference, 2017

Approximate Large-scale Multiple Kernel k-means Using Deep Neural Network.
Proceedings of the Twenty-Sixth International Joint Conference on Artificial Intelligence, 2017

Multiple Kernel Clustering Framework with Improved Kernels.
Proceedings of the Twenty-Sixth International Joint Conference on Artificial Intelligence, 2017

2016
An FPGA Implementation for Solving the Large Single-Source-Shortest-Path Problem.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm.
IEICE Electron. Express, 2015

Efficient graphics processing unit based layered decoders for quasicyclic low-density parity-check codes.
Concurr. Comput. Pract. Exp., 2015

2014
CuSora: Real-time software radio using multi-core graphics processing unit.
J. Syst. Archit., 2014

Efficient Parallel Interference Cancellation MIMO Detector for Software Defined Radio on GPUs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Parallel graph traversal for FPGA.
IEICE Electron. Express, 2014

Supernodal sparse Cholesky factorization on graphics processing units.
Concurr. Comput. Pract. Exp., 2014

Efficient parallel implementation of three-point viterbi decoding algorithm on CPU, GPU, and FPGA.
Concurr. Comput. Pract. Exp., 2014

A high throughput K-best detector on FPGA.
Proceedings of the IEEE International Black Sea Conference on Communications and Networking, 2014

2013
From WiFi to WiMAX: Efficient GPU-based Parameterized Transceiver across Different OFDM Protocols.
KSII Trans. Internet Inf. Syst., 2013

Parallel Sparse Cholesky Factorization on a Heterogeneous Platform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A fully parallel truncated Viterbi decoder for Software Defined Radio on GPUs.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs.
Proceedings of the 14th IEEE Workshop on Signal Processing Advances in Wireless Communications, 2013

2012
Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA.
IEICE Trans. Commun., 2012

CPU-GPU hybrid accelerating the Zuker algorithm for RNA secondary structure prediction applications.
BMC Genom., 2012

2011
A high-throughput reconfigurable Viterbi decoder.
Proceedings of the 2011 International Conference on Wireless Communications & Signal Processing, 2011


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