Rahul Shrestha
Orcid: 0000-0003-2224-0892
According to our database1,
Rahul Shrestha
authored at least 54 papers
between 2012 and 2024.
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Bibliography
2024
A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks.
IEEE Trans. Veh. Technol., September, 2023
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes.
IEEE Trans. Veh. Technol., 2023
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal.
J. Signal Process. Syst., December, 2022
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network.
IEEE Trans. Consumer Electron., 2022
Selective register-file cache: an energy saving technique for embedded processor architecture.
Des. Autom. Embed. Syst., 2022
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network.
IET Circuits Devices Syst., 2018
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
2017
Microprocess. Microsystems, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
2016
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards.
IET Circuits Devices Syst., 2016
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders.
Circuits Syst. Signal Process., 2016
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder.
J. Signal Process. Syst., 2015
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder.
J. Low Power Electron., 2015
Proceedings of the 2015 IEEE Global Humanitarian Technology Conference, 2015
2014
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
2013
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard.
IET Commun., 2013
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder.
Proceedings of the International Conference on Advances in Computing, 2013
2012
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012