Ryo Haga

According to our database1, Ryo Haga authored at least 4 papers between 1995 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2001
Interface socket design methodology to generate embedded DRAM macros.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.
IEEE J. Solid State Circuits, 2000

1998
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.
IEEE J. Solid State Circuits, 1998

1995
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.
IEEE J. Solid State Circuits, November, 1995


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