Tomoaki Yabe

According to our database1, Tomoaki Yabe authored at least 12 papers between 2002 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.
IEEE J. Solid State Circuits, 2014

2012
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.
Proceedings of the Symposium on VLSI Circuits, 2012

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.
IEEE J. Solid State Circuits, 2011

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.
IEEE J. Solid State Circuits, 2010

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-k metal-gate CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 0.7 V Single-Supply SRAM With 0.495 µm<sup>2</sup> Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme.
IEEE J. Solid State Circuits, 2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2002
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002


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