Shinji Miyano

According to our database, Shinji Miyano authored at least 32 papers between 1995 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current.

Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, Takehiko Hojo

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.

Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2013

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy.

Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi

IEEE J. Solid State Circuits, 2013

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.

Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano

IEICE Trans. Electron., 2013

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM.

Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto

IEICE Trans. Electron., 2013

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.

Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.

Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2012

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor.

Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi

IEICE Trans. Electron., 2012

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Electron. Express, 2012

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.

Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara

Proceedings of the Symposium on VLSI Circuits, 2012

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy.

Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.

Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Improvement of Read Margin and Its Distribution by V_TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection.

Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi

IEEE J. Solid State Circuits, 2011

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.

Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM.

Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme.

Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Misleading energy and performance claims in sub/near threshold digital systems.

Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme.

Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 36th European Solid-State Circuits Conference, 2010

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor.

Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications.

Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation.

Tamio Ikehashi, Takayuki Miyazaki, Hiroaki Yamazaki, Atsushi Suzuki, Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A 65nm low-power embedded DRAM with extended data-retention sleep mode.

Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2001

Interface socket design methodology to generate embedded DRAM macros.

Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.

Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata

IEEE J. Solid State Circuits, 2000

1999

Universal Test Interface for Embedded-DRAM Testing.

Shinji Miyano, Katsuhiko Sato, Kenji Numata

IEEE Des. Test Comput., 1999

1998

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.

Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata

IEEE J. Solid State Circuits, 1998

A DRAM module generator with an expandable cell array scheme.

Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1995

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.

Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea

IEEE J. Solid State Circuits, November, 1995