Masaharu Wada

According to our database, Masaharu Wada authored at least 5 papers between 1993 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2008

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications.

Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A 65nm low-power embedded DRAM with extended data-retention sleep mode.

Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1998

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.

Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata

IEEE J. Solid State Circuits, 1998

1995

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.

Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea

IEEE J. Solid State Circuits, November, 1995

1993

Proposal for fully automated mail processing system for the 21st century.

Masaharu Wada

Pattern Recognit. Lett., 1993