S. M. Mayur

According to our database1, S. M. Mayur authored at least 2 papers between 2016 and 2017.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Design of Low Power 5-Bit Hybrid Flash ADC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016


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