M. H. Vasantha

According to our database1, M. H. Vasantha authored at least 42 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design of Approximate Booth Squarer for Error-Tolerant Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Approximate radix-8 Booth multiplier for low power and high speed applications.
Microelectron. J., 2020

IET Circuits, Devices & Systems.
IET Circuits Devices Syst., 2020

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process.
IET Circuits Devices Syst., 2020

Reversible Logic Implementation of Image Denoising for Grayscale Images.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Wideband 12 Phase Ring Oscillator for 5G Applications.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
Ultra-low voltage, power efficient continuous-time filters in 180 nm CMOS technology.
IET Circuits Devices Syst., 2019

Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications.
Proceedings of the TENCON 2019, 2019

Design and Analysis of Energy Efficient Reversible Logic based Full Adder.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Asynchronous Analog to Digital Converter for Video Camera Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Process Corner Calibration for Standard Cell Based Flash ADC.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Two-Step Flash ADC Using Standard Cell Based Flash ADCs.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures.
Wirel. Pers. Commun., 2018

Hardware implementation of fault tolerance NoC core mapping.
Telecommun. Syst., 2018

An energy-efficient fault-aware core mapping in mesh-based network on chip systems.
J. Netw. Comput. Appl., 2018

A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell.
Proceedings of the TENCON 2018, 2018

Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.
Proceedings of the TENCON 2018, 2018

Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Design of Approximate Dividers for Error Tolerant Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

An Asynchronous Analog to Digital Converter for Surveillance Camera Applications.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Performance Enhancement of Split Length Compensated Operational Amplifiers.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design and Analysis of Approximate Multipliers for Error-Tolerant Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Design of Area-Power-Delay Efficient Square Root Carry Select Adder.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
High-performance and energy-efficient fault-tolerance core mapping in NoC.
Sustain. Comput. Informatics Syst., 2017

System level fault-tolerance core mapping and FPGA-based verification of NoC.
Microelectron. J., 2017

A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

High Performance Sense Amplifier Based Flip Flop for Driver Applications.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design of Low Power 5-Bit Hybrid Flash ADC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and Implementation of Tunable Bandpass Filter for Biomedical Applications.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.
Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

2015
Low power, high speed error tolerant multiplier using approximate adders.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2012
0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process.
Proceedings of the International Symposium on Electronic System Design, 2012


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