Siddharth R. K.

According to our database, Siddharth R. K. authored at least 25 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing.

K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin

IEEE Access, 2024

2023

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing.

K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar

IEEE Access, 2023

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process.

Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Approximate Three-Operand Binary Adder for Error-Resilient Applications.

Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS.

R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2021

A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications.

Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications.

Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process.

Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.

Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni

IEEE Trans. Circuits Syst., 2020

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications.

Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha

SN Comput. Sci., 2020

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process.

Siddharth Rajkumar Kala, Sushma Chandaka, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra, Edoardo Bonizzoni

IET Circuits Devices Syst., 2020

A Wideband 12 Phase Ring Oscillator for 5G Applications.

Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications.

Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

A 1.8 V, Mode-Configurable Hybrid Smart ADC.

Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A 1.8 V Quadrature Phase LC Oscillator for 5G Applications.

Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC.

Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

2019

An Asynchronous Analog to Digital Converter for Video Camera Applications.

Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Process Corner Calibration for Standard Cell Based Flash ADC.

Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Two-Step Flash ADC Using Standard Cell Based Flash ADCs.

Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

An Asynchronous Analog to Digital Converter for Surveillance Camera Applications.

Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design of Area-Power-Delay Efficient Square Root Carry Select Adder.

Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications.

Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.

S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing.

Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Design of Low Power 5-Bit Hybrid Flash ADC.

S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016