Saeed Seyedfaraji

According to our database, Saeed Seyedfaraji authored at least 6 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis.

Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman

IEEE Access, 2024

2022

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit.

Saeed Seyedfaraji, Javad Talafy, Mohamed M. Sabry, Semeen Rehman

CoRR, 2022

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit.

Saeed Seyedfaraji, Javad Talafy Daryani, Mohamed M. Sabry Aly, Semeen Rehman

IEEE Access, 2022

SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology.

Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator.

Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2020

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories.

Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi

Microprocess. Microsystems, 2020