Amir M. Hajisadeghi

According to our database, Amir M. Hajisadeghi authored at least 8 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks.

Ali Sedaghatgoo, Amir M. Hajisadeghi, Mahmoud Momtazpour, Nader Bagherzadeh

CoRR, 2024

2022

EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis.

Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics.

Amir M. Hajisadeghi, Hamid R. Zarandi

Microprocess. Microsystems, September, 2021

2020

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories.

Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi

Microprocess. Microsystems, 2020

2019

A Fast and Efficient Fault Tree Analysis Using Approximate Computing.

Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari

Proceedings of the 15th European Dependable Computing Conference, 2019

2018

A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays.

Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits.

Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

DUSTER: DUal Source Write TERmination Method for STT-RAM Memories.

Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018