Saeideh Nabipour

Orcid: 0000-0002-3622-1513

According to our database1, Saeideh Nabipour authored at least 9 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing.
Proceedings of the 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2026

2025
Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.
J. Circuits Syst. Comput., 2025

Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design.
Proceedings of the 55th IEEE International Symposium on Multiple-Valued Logic, 2025

Fast and Scalable MAGIC-Based Wallace Tree Multiplier for In-Memory Computing.
Proceedings of the 2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2025

2023
Arithmetic Operators over Finite Field GF(2<sup>m</sup>) for Error Correction Codes Application.
CoRR, 2023

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m).
CoRR, 2023

2021
Fast BCH Coding for Optimal Robust Image Watermarking in DCT Domain.
CoRR, 2021

Area-Delay-Efficeint FPGA Design of 32-bit Euclid's GCD based on Sum of Absolute Difference.
CoRR, 2021

2020
Multimodal price prediction.
CoRR, 2020


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