Salvador Pinillos Gimenez

Orcid: 0000-0002-3616-9559

According to our database1, Salvador Pinillos Gimenez authored at least 16 papers between 2003 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Optimizing RGB Lighting for Lettuce Growth in Vertical Farms With Bio-Inspired Optimization Algorithm.
IEEE Internet Things J., 2026

An Unsupervised Learning Approach to Validate the Robustness of Octagonal MOSFETs in X-Ray Environments.
IEEE Access, 2026

2025
Longitudinal Crop Characteristics for Different Lighting Conditions in a Vertical Farm.
Dataset, April, 2025

Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence.
Appl. Soft Comput., 2025

2019
A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs.
Microelectron. J., 2019

A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems.
IEEE Embed. Syst. Lett., 2019

Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

2018
Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017
Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

VI-Based Measurement System Focusing on Space Applications.
J. Electron. Test., 2017

2016
Layout Techniques for MOSFETs
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, ISBN: 978-3-031-02031-5, 2016

From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design.
Int. J. High Perform. Syst. Archit., 2016

2015
Diamond layout style impact on SOI MOSFET in high temperature environment.
Microelectron. Reliab., 2015

2006
Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS.
Microelectron. J., 2006

2003
Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003


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