Samed Maltabas

According to our database1, Samed Maltabas authored at least 8 papers between 2009 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
An IDDQ BIST approach to characterize phase-locked loop parameters.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
Novel Practical Built-in Current Sensors.
J. Electron. Test., 2012

Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Power minimization methodology for VCTL topologies.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A new built-in IDDQ testing method using programmable BICS.
Proceedings of the 15th European Test Symposium, 2010

2009
Varicap threshold logic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009


  Loading...