Samiha Mourad

According to our database1, Samiha Mourad authored at least 41 papers between 1980 and 2012.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2008, "For contributions to fault modeling in digital circuits and systems".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
A low-cost configurability test strategy for an embedded analog circuit.
Microelectron. J., 2012

2010
Partial-Matching Technique in a Mixed-Mode BIST Environment.
IEEE Trans. Instrum. Meas., 2010

Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2008
Wave Pipelining Using Self Reset Logic.
VLSI Design, 2008

2006
Crosstalk Induced Fault Analysis and Test in DRAMs.
J. Electron. Test., 2006

Wave Pipelining using Self Reset Logic.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

BCH-based Compactors of Test Responses with Controllable Masks.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Self-reset logic for fast arithmetic applications.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Design-for-testability for embedded delay-locked loops.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Embedded test control schemes using iBIST for SOCs.
IEEE Trans. Instrum. Meas., 2005

2004
On-chip rise-time measurement.
IEEE Trans. Instrum. Meas., 2004

Crosstalk induced fault analysis in DRAMs.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
A self-binning BIST structure for data communications transceivers.
IEEE Trans. Instrum. Meas., 2003

2002
A framework for the characterization and verification of embedded phase-locked loops.
IEEE Trans. Instrum. Meas., 2002

Partial Scan Testing on the Register-Transfer Level.
J. Electron. Test., 2002

Embedded testing for data communications circuits.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A new model for metastability.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Embedded test control schemes for compression in SOCs.
Proceedings of the 39th Design Automation Conference, 2002

2001
Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates.
VLSI Design, 2001

Compression Technique for Interactive BIST Application.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Verification of Embedded Phase-Locked Loops.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

At-speed testing of data communications transceivers.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Crosstalk in Deep Submicron DRAMs.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Performance of submicron CMOS devices and gates with substrate biasing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Scan-path based testing of systems on a chip.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1996
Digital design with minimal number of scan flip-flops.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994
Gate-to-channel shorts in BiCMOS logic gates.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Modeling the Effect of Ground Bounce on Noise Margin.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Optimal Logic Blocks for FPGAs, using Factorial Design Techniques.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Computer-Aided Testing Systems: Evaluation and Benchmark Circuits.
VLSI Design, 1993

1992
Benchmarking Array Comparators.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1990
Sequential circuit testing.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1988
Probability models for pseudorandom test sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On Benchmarking Digital Testing Systems.
Proceedings of the Proceedings International Test Conference 1988, 1988

Digital Testing, Theory and Practice.
Proceedings of the Proceedings International Test Conference 1988, 1988

Multiple stuck-at fault testability of self-testing checkers.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
On the Reliability of the IBM MVS/XA Operating.
IEEE Trans. Software Eng., 1987

1986
Stuck-At Fault Detection in Parity Trees.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

Multiple Fault Detection in Parity Trees.
Proceedings of the Spring COMPCON'86, 1986

1985
An Experimental Study Comparing 74LS181 Test Sets.
Proceedings of the Spring COMPCON'85, 1985

1980
An optimized ATPG.
Proceedings of the 17th Design Automation Conference, 1980


  Loading...