Sampo Tuuna

According to our database1, Sampo Tuuna authored at least 10 papers between 2003 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Modeling of Energy Dissipation in RLC Current-Mode Signaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses.
IET Comput. Digit. Tech., 2012

2011
Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.
IET Circuits Devices Syst., 2011

2008
Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling.
VLSI Design, 2007

2006
Analytical model for crosstalk and intersymbol interference in point-to-point buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects.
Proceedings of the International Symposium on System-on-Chip, 2006

2003
Estimation of Crosstalk Noise for On-Chip Buses.
Proceedings of the Integrated Circuit and System Design, 2003


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