Juha Plosila

According to our database1, Juha Plosila authored at least 247 papers between 1997 and 2021.

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Bibliography

2021
Energy-Efficient Navigation of an Autonomous Swarm with Adaptive Consciousness.
Remote. Sens., 2021

Cellular Formation Maintenance and Collision Avoidance Using Centroid-Based Point Set Registration in a Swarm of Drones.
CoRR, 2021

High-Performance Parallel Fault Simulation for Multi-Core Systems.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems.
Proceedings of the 26th IEEE European Test Symposium, 2021

MCX ? An Open-Source Framework For Digital Twins.
Proceedings of the 35th International ECMS International Conference on Modelling and Simulation, 2021

Applications of Internet of Things (IoT) in Agriculture - The Potential and Challenges in Smart Farm in Uganda.
Proceedings of the International Conference on Artificial Intelligence and Computer Vision, 2021

2020
Swarm Formation Morphing for Congestion Aware Collision Avoidance.
CoRR, 2020

Night vision obstacle detection and avoidance based on Bio-Inspired Vision Sensors.
CoRR, 2020

Dynamic Formation Reshaping Based on Point Set Registration in a Swarm of Drones.
CoRR, 2020

GeFeS: A generalized wrapper feature selection approach for optimizing classification performance.
Comput. Biol. Medicine, 2020

Energy-Efficient Formation Morphing for Collision Avoidance in a Swarm of Drones.
IEEE Access, 2020

Unmanned Aerial Vehicles (UAVs): Collision Avoidance Systems and Approaches.
IEEE Access, 2020

Comparison of Linear and Nonlinear Methods for Distributed Control of a Hierarchical Formation of UAVs.
IEEE Access, 2020

Heterogeneous Parallelization for Object Detection and Tracking in UAVs.
IEEE Access, 2020

Enhancing Smart Grids via Advanced Metering Infrastructure and Fog Computing Fusion.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Navigation of Autonomous Swarm of Drones Using Translational Coordinates.
Proceedings of the Advances in Practical Applications of Agents, Multi-Agent Systems, and Trustworthiness. The PAAMS Collection, 2020

IoT Protocol Selection for Smart Grid Applications: Merging Qualitative and Quantitative Metrics.
Proceedings of the 43rd International Convention on Information, 2020

Asynchronous Corner Tracking Algorithm Based on Lifetime of Events for DAVIS Cameras.
Proceedings of the Advances in Visual Computing - 15th International Symposium, 2020

Dynamic Resource-Aware Corner Detection for Bio-Inspired Vision Sensors.
Proceedings of the 25th International Conference on Pattern Recognition, 2020

Navigation System For Landing A Swarm Of Autonomous Drones On A Movable Surface.
Proceedings of the 34th International ECMS Conference on Modelling and Simulation, 2020

Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Towards Real-Time Edge Detection for Event Cameras Based on Lifetime and Dynamic Slicing.
Proceedings of the International Conference on Artificial Intelligence and Computer Vision, 2020

2019
Energy-Aware VM Consolidation in Cloud Data Centers Using Utilization Prediction Model.
IEEE Trans. Cloud Comput., 2019

A Survey on Odometry for Autonomous Navigation Systems.
IEEE Access, 2019

Machine Learning for sEMG Facial Feature Characterization.
Proceedings of the Signal Processing: Algorithms, 2019

Formation Maintenance and Collision Avoidance in a Swarm of Drones.
Proceedings of the ISCSIC 2019: 3rd International Symposium on Computer Science and Intelligent Control, 2019

Monocular visual odometry based on hybrid parameterization.
Proceedings of the Twelfth International Conference on Machine Vision, 2019

A Qualitative Comparison Model for Application Layer IoT Protocols.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019

2018
Parallel imperialist competitive algorithms.
Concurr. Comput. Pract. Exp., 2018

An Efficient Multi-sensor Fusion Approach for Object Detection in Maritime Environments.
Proceedings of the 21st International Conference on Intelligent Transportation Systems, 2018

Virtualization at the network edge: A technology perspective.
Proceedings of the Third International Conference on Fog and Mobile Edge Computing, 2018

2017
Hierarchal Placement of Smart Mobile Access Points in Wireless Sensor Networks Using Fog Computing.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

A reliable weighted feature selection for auto medical diagnosis.
Proceedings of the 15th IEEE International Conference on Industrial Informatics, 2017

A Security Framework for Fog Networks Based on Role-Based Access Control and Trust Models.
Proceedings of the Research and Practical Issues of Enterprise Information Systems, 2017

2016
Polymorphic Configuration Architecture for CGRAs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures.
IEEE Trans. Computers, 2016

Placement of Smart Mobile Access Points in Wireless Sensor Networks and Cyber-Physical Systems Using Fog Computing.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

PICA: Multi-population Implementation of Parallel Imperialist Competitive Algorithms.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

SEECC: A secure and efficient elliptic curve cryptosystem for E-health applications.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Multi-population parallel imperialist competitive algorithm for solving systems of nonlinear equations.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

An Approach for Smart Management of Big Data in the Fog Computing Context.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

2015
Using Ant Colony System to Consolidate VMs for Green Cloud Computing.
IEEE Trans. Serv. Comput., 2015

In-order delivery approach for 2D and 3D NoCs.
J. Supercomput., 2015

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs.
Microprocess. Microsystems, 2015

Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.
ACM J. Emerg. Technol. Comput. Syst., 2015

PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems.
Concurr. Comput. Pract. Exp., 2015

DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs.
Proceedings of the 28th International Conference on VLSI Design, 2015

Message from the chairs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Parallel Implementation of Fuzzified Pattern Matching Algorithm on GPU.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

FIST: A Framework to Interleave Spiking Neural Networks on CGRAs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Power-aware online testing of manycore systems in the dark silicon era.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Utilization Prediction Aware VM Consolidation Approach for Green Cloud Computing.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014
Special section on advances in methods for adaptive multicore systems.
J. Supercomput., 2014

Adaptive load balancing in learning-based approaches for many-core embedded systems.
J. Supercomput., 2014

Editorial: Special issue on design challenges for many-core processors.
ACM Trans. Embed. Comput. Syst., 2014

High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform.
IEEE Trans. Computers, 2014

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014

Deadlock free routing algorithm for minimizing congestion in a Hamiltonian connected recursive 3D-NoCs.
Microelectron. J., 2014

Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs.
Microprocess. Microsystems, 2014

Special issue on many-core embedded systems.
Microprocess. Microsystems, 2014

High Performance Pattern Matching on Heterogeneous Platform.
J. Integr. Bioinform., 2014

Private reliability environments for efficient fault-tolerance in CGRAs.
Des. Autom. Embed. Syst., 2014

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Multi Rectangle Modeling Approach for Application Mapping on a Many-Core System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Energy-Efficient Virtual Machines Consolidation in Cloud Data Centers Using Reinforcement Learning.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Integration of AES on Heterogeneous Many-Core System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Heterogeneous Parallelization of Aho-Corasick Algorithm.
Proceedings of the 8th International Conference on Practical Applications of Computational Biology & Bioinformatics, 2014

Silicon synapse designs for VLSI neuromorphic platform.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Dark silicon aware power management for manycore systems under dynamic workloads.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

NeuroCGRA: A CGRA with support for neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Exploring NoC jitter effect on simulation of spiking neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

TransPar: Transformation based dynamic Parallelism for low power CGRAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Multi-agent Based Architecture for Dynamic VM Consolidation in Cloud Data Centers.
Proceedings of the 40th EUROMICRO Conference on Software Engineering and Advanced Applications, 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Parameterized AES-Based Crypto Processor for FPGAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Energy-efficient concurrent testing approach for many-core systems in the dark silicon age.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Online testing of many-core systems in the Dark Silicon era.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

From self-aware building blocks to self-organizing systems with hierarchical agent-based adaptation.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Hierarchical VM Management Architecture for Cloud Data Centers.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

Adjustable contiguity of run-time task allocation in networked many-core systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Positioning Antifragility for Clouds on Public Infrastructures.
Proceedings of the 5th International Conference on Ambient Systems, 2014

Hierarchical Agent-Based Architecture for Resource Management in Cloud Data Centers.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

Energy-Aware Dynamic VM Consolidation in Cloud Data Centers Using Ant Colony System.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

2013
Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip.
Microprocess. Microsystems, 2013

Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip.
Microprocess. Microsystems, 2013

Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes.
Microprocess. Microsystems, 2013

Optimal placement of vertical connections in 3D Network-on-Chip.
J. Syst. Archit., 2013

Design space exploration of thermal-aware many-core systems.
J. Syst. Archit., 2013

Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip.
J. Syst. Archit., 2013

A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.
J. Syst. Archit., 2013

Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels.
J. Comput. Syst. Sci., 2013

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.
J. Comput. Syst. Sci., 2013

Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems.
Int. J. Adapt. Resilient Auton. Syst., 2013

Energy Aware Consolidation Algorithm Based on K-Nearest Neighbor Regression for Cloud Data Centers.
Proceedings of the IEEE/ACM 6th International Conference on Utility and Cloud Computing, 2013

Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Towards a Configurable Many-core Accelerator for FPGA-based embedded systems.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

PDNOC: An Efficient Partially Diagonal Network-on-Chip Design.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

Hierarchical Supporting Structure for Dynamic Organization in Many-core Computing Systems.
Proceedings of the PECCS 2013, 2013

Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access.
Proceedings of the Parallel Computing Technologies - 12th International Conference, 2013

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

From traditional VLSI education to embedded electronics.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Efficient application mapping in resource limited homogeneous NoC-based manycore systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

FPGA implementation of AES-based crypto processor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

LiRCUP: Linear Regression Based CPU Usage Prediction Algorithm for Live Migration of Virtual Machines in Data Centers.
Proceedings of the 39th Euromicro Conference on Software Engineering and Advanced Applications, 2013

Generation of Structural VHDL Code with Library Components from Formal Event-B Models.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy.
Proceedings of the Design, Automation and Test in Europe, 2013

CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Smart hill climbing for agile dynamic mapping in many-core systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Optimized multicore architectures for data parallel fast Fourier transform.
Proceedings of the Computer Systems and Technologies, 2013

MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration.
Proceedings of the Computer Systems and Technologies, 2013

MD: Minimal path-based fault-tolerant routing in on-Chip Networks.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Private configuration environments (PCE) for efficient reconfiguration, in CGRAs.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Memory-Efficient On-Chip Network With Adaptive Interfaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.
J. Low Power Electron., 2012

Adaptive Input-Output Selection Based On-Chip Router Architecture.
J. Low Power Electron., 2012

Status Data and Communication Aspects in Dynamically Clustered Network-on-Chip Monitoring.
J. Electr. Comput. Eng., 2012

Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip.
Int. J. Embed. Real Time Commun. Syst., 2012

Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability.
Int. J. Embed. Real Time Commun. Syst., 2012

Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study.
Int. J. Adapt. Resilient Auton. Syst., 2012

Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip.
IET Circuits Devices Syst., 2012

Exploration of heuristic scheduling algorithms for 3D multicore processors.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Adaptive reinforcement learning method for networks-on-chip.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Transport layer aware design of network interface in many-core systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Optimized Q-learning model for distributing traffic in on-Chip Networks.
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

Dual Congestion Awareness scheme in On-Chip Networks.
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

A high-efficiency low-cost heterogeneous 3D network-on-chip design.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Analysis of Power Management Strategies for a Single-Chip Cloud Computer.
Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2012

Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip.
Proceedings of the Learning and Intelligent Optimization - 6th International Conference, 2012

Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication.
Proceedings of the International SoC Design Conference, 2012

An efficient history-based routing algorithm for interconnection networks.
Proceedings of the International SoC Design Conference, 2012

CoNA: Dynamic application mapping for congestion reduction in many-core systems.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Vertical and horizontal integration towards collective adaptive system: a visionary approach.
Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012

Existing challenges and new opportunities in context-aware systems.
Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012

Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

t(k)-SA: accelerated simulated annealing algorithm for application mapping on networks-on-chip.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

NoC-AXI interface for FPGA-based MPSoC platforms.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

HLS-DoNoC: High-level simulator for dynamically organizational NoCs.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach.
Int. J. Embed. Real Time Commun. Syst., 2011

Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.
IET Circuits Devices Syst., 2011

Agent-based on-chip network using efficient selection method.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Exploration of MPSoC monitoring and management systems.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Efficient congestion-aware selection method for on-chip networks.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

High-performance on-chip network platform for memory-on-processor architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Analysis of Status Data Update in Dynamically Clustered Network-on-chip Monitoring.
Proceedings of the PECCS 2011, 2011

Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.
Proceedings of the PECCS 2011, 2011

A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A fault-tolerant and hierarchical routing algorithm for NoC architectures.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.
Proceedings of the NOCS 2011, 2011

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.
Proceedings of the NOCS 2011, 2011

Q-learning based congestion-aware routing algorithm for on-chip network.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Thermal Analysis of Advanced 3D Stacked Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Power-Efficient Inter-Layer Communication Architectures for 3D NoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Cluster-based topologies for 3D stacked architectures.
Proceedings of the 8th Conference on Computing Frontiers, 2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

HIBS - Novel inter-layer bus structure for stacked architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Modeling Communication in Multi-Processor Systems-on-Chip Using Modular Connectors.
Int. J. Embed. Real Time Commun. Syst., 2010

Current Challenges in Embedded Communication Systems.
Int. J. Embed. Real Time Commun. Syst., 2010

Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification.
Int. J. Embed. Real Time Commun. Syst., 2010

Thermal modelling of 3D multicore systems in a flip-chip package.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A Low-Latency and Memory-Efficient On-chip Network.
Proceedings of the NOCS 2010, 2010

BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

High-Performance TSV Architecture for 3-D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Input-Output Selection Based Router for Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Heap access optimizations for a hardware-accelerated Java virtual machine.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Process variation tolerant on-chip communication using receiver and driver reconfiguration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Tree-model based mapping for energy-efficient and low-latency Network-on-Chip.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.
Proceedings of the 7th Conference on Computing Frontiers, 2010

CMIT - A novel cluster-based topology for 3D stacked architectures.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Self-timed thermal sensing and monitoring of multicore systems.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Power Aware System Refinement.
Electron. Notes Theor. Comput. Sci., 2008

Area efficient delay-insensitive and differential current sensing on-chip interconnect.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A novel hardware acceleration scheme for java method calls.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Rigorous Communication Modelling at Transaction Level With Systemc.
Proceedings of the ICSOFT 2008, 2008

2007
High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling.
VLSI Design, 2007

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC.
VLSI Design, 2007

Time Aware System Refinement.
Electron. Notes Theor. Comput. Sci., 2007

Analysis of forward error correction methods for nanoscale networks-on-chip.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

FPGA Prototype of the REALJava Co-Processor.
Proceedings of the International Symposium on System-on-Chip, 2007

Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fault Tolerance Analysis of NoC Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.
Proceedings of the Seventh International Conference on Parallel and Distributed Computing, 2006

Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Formal Modelling of Multiclocked SoC Systems.
Proceedings of the International Symposium on System-on-Chip, 2006

Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.
Proceedings of the International Symposium on System-on-Chip, 2006

Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects.
Proceedings of the International Symposium on System-on-Chip, 2006

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An approach for analysing and improving fault tolerance in radio architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Time Aware Modelling and Analysis of Multiclocked VLSI Systems.
Proceedings of the Formal Methods and Software Engineering, 2006

2005
Asynchronous system synthesis.
Sci. Comput. Program., 2005

Formal Specification of a Protocol Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2005

On-chip Debug for an Asynchronous Java Accelerator.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Formal Modelling of Synchronous Hardware Components for System-on-Chip.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Towards a Formal Power Estimation Framework for Hardware Systems.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Instruction Folding for an Asynchronous Java Co-Processor.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Reliable Asynchronous Links for SoC.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Modelling and Refinement of an On-Chip Communication Architecture.
Proceedings of the Formal Methods and Software Engineering, 2005

2004
Self-timed communication platform for implementing high-performance systems-on-chip.
Integr., 2004

Refinement of on-chip communication channels.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Constituent Elements of a Correctness-Preserving UML Design Approach.
Proceedings of the Integrated Formal Methods, 4th International Conference, 2004

2003
Implementation of a Self-Timed Segmented Bus.
IEEE Des. Test Comput., 2003

Modeling on-chip communication.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Interconnect peak current reduction for wavelet array processor using self-timed signaling.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Specification of an Asynchronous On-chip Bus.
Proceedings of the Formal Methods and Software Engineering, 2002

Design with Asynchronously Communicating Components.
Proceedings of the Formal Methods for Components and Objects, 2002

2001
Asynchronous interface for locally clocked modules in ULSI systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Formal Pipeline Design.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Design of Synchronous Action Systems.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1997
Action Systems in Pipelined Processor Design.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997


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