Hannu Tenhunen

According to our database1, Hannu Tenhunen authored at least 416 papers between 1991 and 2021.

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Bibliography

2021
Real time performance analysis of secure IoT protocols for microgrid communication.
Future Gener. Comput. Syst., 2021

2020
Night vision obstacle detection and avoidance based on Bio-Inspired Vision Sensors.
CoRR, 2020

Dynamic Resource-aware Corner Detection for Bio-inspired Vision Sensors.
CoRR, 2020

Dynamic Formation Reshaping Based on Point Set Registration in a Swarm of Drones.
CoRR, 2020

Collaborative Multi-Robot Systems for Search and Rescue: Coordination and Perception.
CoRR, 2020

GeFeS: A generalized wrapper feature selection approach for optimizing classification performance.
Comput. Biol. Medicine, 2020

Energy-Efficient Formation Morphing for Collision Avoidance in a Swarm of Drones.
IEEE Access, 2020

Unmanned Aerial Vehicles (UAVs): Collision Avoidance Systems and Approaches.
IEEE Access, 2020

Collaborative Multi-Robot Search and Rescue: Planning, Coordination, Perception, and Active Vision.
IEEE Access, 2020

Beam-width Agile antenna for 5G MMW Applications.
Proceedings of the 2020 International Conference on UK-China Emerging Technologies, 2020

Towards Active Vision with UAVs in Marine Search and Rescue: Analyzing Human Detection at Variable Altitudes.
Proceedings of the 2020 IEEE International Symposium on Safety, 2020

Navigation of Autonomous Swarm of Drones Using Translational Coordinates.
Proceedings of the Advances in Practical Applications of Agents, Multi-Agent Systems, and Trustworthiness. The PAAMS Collection, 2020

Asynchronous Corner Tracking Algorithm Based on Lifetime of Events for DAVIS Cameras.
Proceedings of the Advances in Visual Computing - 15th International Symposium, 2020

Lightweight Security Algorithms for Resource-constrained IoT-based Sensor Nodes.
Proceedings of the 2020 IEEE International Conference on Communications, 2020

Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Towards Real-Time Edge Detection for Event Cameras Based on Lifetime and Dynamic Slicing.
Proceedings of the International Conference on Artificial Intelligence and Computer Vision, 2020

2019
Energy-Aware VM Consolidation in Cloud Data Centers Using Utilization Prediction Model.
IEEE Trans. Cloud Comput., 2019

Low-Rank Multi-Channel Features for Robust Visual Object Tracking.
Symmetry, 2019

A Demand-Response Scheme Using Multi-Agent System for Smart DC Microgrid.
Int. J. Embed. Real Time Commun. Syst., 2019

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard.
Int. J. Embed. Real Time Commun. Syst., 2019

Novel QR-incorporated chipless RFID tag.
IEICE Electron. Express, 2019

Towards an interoperable Internet of Things through a web of virtual things at the Fog layer.
Future Gener. Comput. Syst., 2019

Energy efficient fog-assisted IoT system for monitoring diabetic patients with cardiovascular disease.
Future Gener. Comput. Syst., 2019

Orientation Independent Chipless RFID Tag Using Novel Trefoil Resonators.
IEEE Access, 2019

Buffer-Aided Successive Relay Selection Scheme for Energy Harvesting IoT Networks.
IEEE Access, 2019

Robustness-Driven Hybrid Descriptor for Noise-Deterrent Texture Classification.
IEEE Access, 2019

An Integrated Antenna System for 4G and Millimeter-Wave 5G Future Handheld Devices.
IEEE Access, 2019

A Survey on Odometry for Autonomous Navigation Systems.
IEEE Access, 2019

Texture Representation Through Overlapped Multi-Oriented Tri-Scale Local Binary Pattern.
IEEE Access, 2019

Edge-AI in LoRa-based Health Monitoring: Fall Detection System with Fog Computing and LSTM Recurrent Neural Networks.
Proceedings of the 42nd International Conference on Telecommunications and Signal Processing, 2019

Distributed Progressive Formation Control with One-Way Communication for Multi-Agent Systems.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2019

Machine Learning for sEMG Facial Feature Characterization.
Proceedings of the Signal Processing: Algorithms, 2019

Collaborative Mapping with IoE-based Heterogeneous Vehicles for Enhanced Situational Awareness.
Proceedings of the IEEE Sensors Applications Symposium, 2019

Artificial Intelligence at the Edge in the Blockchain of Things.
Proceedings of the Wireless Mobile Communication and Healthcare, 2019

Formation Maintenance and Collision Avoidance in a Swarm of Drones.
Proceedings of the ISCSIC 2019: 3rd International Symposium on Computer Science and Intelligent Control, 2019

Detecting Water Reflection Symmetries in Point Clouds for Camera Position Calibration in Unmanned Surface Vehicles.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

Implementation of a Fuel Estimation Algorithm on SoC FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Monocular visual odometry based on hybrid parameterization.
Proceedings of the Twelfth International Conference on Machine Vision, 2019

Edge Computing for Mobile Robots: Multi-Robot Feature-Based Lidar Odometry with FPGAs.
Proceedings of the Twelfth International Conference on Mobile Computing and Ubiquitous Network, 2019

Visual Odometry Offloading in Internet of Vehicles with Compression at the Edge of the Network.
Proceedings of the Twelfth International Conference on Mobile Computing and Ubiquitous Network, 2019

Lossless Compression Techniques in Edge Computing for Mission-Critical Applications in the IoT.
Proceedings of the Twelfth International Conference on Mobile Computing and Ubiquitous Network, 2019

A Survey on LoRa for IoT: Integrating Edge Computing.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019

A Qualitative Comparison Model for Application Layer IoT Protocols.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019

Tri-Band Antenna Array with Defected Ground Structure for mm-Wave 5G Applications.
Proceedings of the IEEE 4th International Conference on Computer and Communication Systems, 2019

Communication-free and Index-free Distributed Formation Control Algorithm for Multi-robot Systems.
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019

Edge AI in Smart Farming IoT: CNNs at the Edge and Fog Computing with LoRa.
Proceedings of the 2019 IEEE AFRICON, Accra, Ghana, September 25-27, 2019, 2019

2018
IoT-Based Remote Pain Monitoring System: From Device to Cloud Platform.
IEEE J. Biomed. Health Informatics, 2018

Energy efficient wearable sensor node for IoT-based fall detection systems.
Microprocess. Microsystems, 2018

Parallel imperialist competitive algorithms.
Concurr. Comput. Pract. Exp., 2018

Fog Computing Approach for Mobility Support in Internet-of-Things Systems.
IEEE Access, 2018

A 3D Tiled Low Power Accelerator for Convolutional Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Hardware-in-Loop Simulation of DC Microgrid using Multi-Agent Systems.
Proceedings of the 22nd Conference of Open Innovations Association, 2018

Wearable in Cloud.
Proceedings of the Third IEEE/ACM International Conference on Connected Health: Applications, 2018

2017
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Performance/Reliability-Aware Resource Management for Many-Cores in Dark Silicon Era.
IEEE Trans. Computers, 2017

Special issue on energy efficient multi-core and many-core systems, Part II.
J. Parallel Distributed Comput., 2017

Internet of things for remote elderly monitoring: a study from user-centered perspective.
J. Ambient Intell. Humaniz. Comput., 2017

Interactive UHF/UWB RFID tag for mass customization.
Inf. Syst. Frontiers, 2017

Communication and Security Technologies for Smart Grid.
Int. J. Embed. Real Time Commun. Syst., 2017

Dual-polarized chipless humidity sensor tag.
IEICE Electron. Express, 2017

Highly-dense flexible chipless RFID tag.
IEICE Electron. Express, 2017

Novel T-shaped resonator based chipless RFID tag.
IEICE Electron. Express, 2017

Triangular loop resonator based compact chipless RFID tag.
IEICE Electron. Express, 2017

FSS inspired polarization insensitive chipless RFID tag.
IEICE Electron. Express, 2017

Directly printable compact chipless RFID tag for humidity sensing.
IEICE Electron. Express, 2017

Frequency signatured directly printable humidity sensing tag using organic electronics.
IEICE Electron. Express, 2017

A 2.4-GHz ISM RF and UWB hybrid RFID real-time locating system for industrial enterprise Internet of Things.
Enterp. Inf. Syst., 2017

Can Dark Silicon Be Exploited to Prolong System Lifetime?
IEEE Des. Test, 2017

A Power management scheme for wirelessly-powered RFID tags with inkjet-printed display.
Proceedings of the IEEE International Conference on RFID Technology & Application, 2017

Hierarchal Placement of Smart Mobile Access Points in Wireless Sensor Networks Using Fog Computing.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Low-cost fog-assisted health-care IoT system with energy-efficient sensor nodes.
Proceedings of the 13th International Wireless Communications and Mobile Computing Conference, 2017

Low-latency hardware architecture for cipher-based message authentication code.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A reliable weighted feature selection for auto medical diagnosis.
Proceedings of the 15th IEEE International Conference on Industrial Informatics, 2017

Rethinking 'Things' - Fog Layer Interplay in IoT: A Mobile Code Approach.
Proceedings of the Research and Practical Issues of Enterprise Information Systems, 2017

A Security Framework for Fog Networks Based on Role-Based Access Control and Trust Models.
Proceedings of the Research and Practical Issues of Enterprise Information Systems, 2017

Autonomous Patient/Home Health Monitoring Powered by Energy Harvesting.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

A framework for load shedding and demand response in DC microgrid using multi agent system.
Proceedings of the 21st Conference of Open Innovations Association, 2017

Towards Moisture Sensing Using Dual-Polarized Printable Chipless RFID Tag.
Proceedings of the 2017 International Conference on Frontiers of Information Technology, 2017

Smart energy efficient gateway for Internet of mobile things.
Proceedings of the 14th IEEE Annual Consumer Communications & Networking Conference, 2017

From threads to events: Adapting a lightweight middleware for Contiki OS.
Proceedings of the 14th IEEE Annual Consumer Communications & Networking Conference, 2017

DoS-IL: A Domain Specific Internet of Things Language for Resource Constrained Devices.
Proceedings of the 8th International Conference on Ambient Systems, 2017

IoT-based continuous glucose monitoring system: A feasibility study.
Proceedings of the 8th International Conference on Ambient Systems, 2017

2016
Polymorphic Configuration Architecture for CGRAs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures.
IEEE Trans. Computers, 2016

Special issue on energy efficient multi-core and many-core systems, Part I.
J. Parallel Distributed Comput., 2016

LISA 2.0: lightweight internet of things service bus architecture using node centric networking.
J. Ambient Intell. Humaniz. Comput., 2016

16-bit frequency signatured directly printable tag for organic electronics.
IEICE Electron. Express, 2016

End-to-end security scheme for mobility enabled healthcare Internet of Things.
Future Gener. Comput. Syst., 2016

Placement of Smart Mobile Access Points in Wireless Sensor Networks and Cyber-Physical Systems Using Fog Computing.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

IoT-based remote facial expression monitoring system with sEMG signal.
Proceedings of the IEEE Sensors Applications Symposium, 2016

QoS based RFID system for smart assembly workshop.
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2016

IoT-based fall detection system with energy efficient sensor nodes.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Chipless RFID tag for IoT applications.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Energy-Efficient IoT-Enabled Fall Detection System with Messenger-Based Notification.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Enhancing the Early Warning Score System Using Data Confidence.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

SEECC: A secure and efficient elliptic curve cryptosystem for E-health applications.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Multi-population parallel imperialist competitive algorithm for solving systems of nonlinear equations.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Approximation knob: power capping meets energy efficiency.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Chipless slot resonators for IoT system identification.
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

Self-aware Early Warning Score System for IoT-Based Personalized Healthcare.
Proceedings of the eHealth 360°, 2016

A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An Approach for Smart Management of Big Data in the Fog Computing Context.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

2015
Using Ant Colony System to Consolidate VMs for Green Cloud Computing.
IEEE Trans. Serv. Comput., 2015

Zero-load predictive model for performance analysis in deflection routing NoCs.
Microprocess. Microsystems, 2015

Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.
ACM J. Emerg. Technol. Comput. Syst., 2015

Special Issue on Emerging Many-Core Systems for Exascale Computing.
ACM J. Emerg. Technol. Comput. Syst., 2015

Frequency signature chipless RFID tag with enhanced data capacity.
IEICE Electron. Express, 2015

PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems.
Concurr. Comput. Pract. Exp., 2015

DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs.
Proceedings of the 28th International Conference on VLSI Design, 2015

Fault tolerant and scalable IoT-based architecture for health monitoring.
Proceedings of the IEEE Sensors Applications Symposium, 2015

Optimization on guard time and synchronization cycle for TDMA-based deterministic RFID system.
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2015

FIST: A Framework to Interleave Spiking Neural Networks on CGRAs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Automated Power and Latency Management in Heterogeneous 3D NoCs.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

Predictable Application Mapping for Manycore Real-Time and Cyber-Physical Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Elderly Monitoring System with Sleep and Fall Detector.
Proceedings of the Internet of Things. IoT Infrastructures, 2015

Context-Aware Early Warning System for In-Home Healthcare Using Internet-of-Things.
Proceedings of the Internet of Things. IoT Infrastructures, 2015

Low Complexity Burst Packet Detection for Wireless-Powered UWB RFID Systems.
Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015

High-Throughput and High-Efficiency Multiple Access Scheme for IEEE802.15.4 Based RFID Sensing.
Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015

Dark silicon aware runtime mapping for many-core systems: A patterning approach.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

A programmable low power current source for bioimpedance measurement: Towards a wearable personalized health assistant.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Software-based on-chip thermal sensor calibration for DVFS-enabled many-core systems.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Adaptive fault simulation on many-core microprocessor systems.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Power-aware online testing of manycore systems in the dark silicon era.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Smart e-Health Gateway: Bringing intelligence to Internet-of-Things based ubiquitous healthcare systems.
Proceedings of the 12th Annual IEEE Consumer Communications and Networking Conference, 2015

A 180 nm-CMOS Asymmetric UWB-RFID Tag with Real-time Remote-monitored ECG-sensing.
Proceedings of the BIODEVICES 2015, 2015

A Smart Catheter System for Minimally Invasive Brain Monitoring.
Proceedings of the BIODEVICES 2015, 2015

LISA: Lightweight Internet of Things Service Bus Architecture.
Proceedings of the 6th International Conference on Ambient Systems, 2015

SEA: A Secure and Efficient Authentication and Authorization Architecture for IoT-Based Healthcare Using Smart Gateways.
Proceedings of the 6th International Conference on Ambient Systems, 2015

Utilization Prediction Aware VM Consolidation Approach for Green Cloud Computing.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

Session Resumption-Based End-to-End Security for Healthcare Internet-of-Things.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

Facial Expression Recognition with sEMG Method.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

Fog Computing in Healthcare Internet of Things: A Case Study on ECG Feature Extraction.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Special section on advances in methods for adaptive multicore systems.
J. Supercomput., 2014

High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform.
IEEE Trans. Computers, 2014

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014

Private reliability environments for efficient fault-tolerance in CGRAs.
Des. Autom. Embed. Syst., 2014

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Multi Rectangle Modeling Approach for Application Mapping on a Many-Core System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Integration of AES on Heterogeneous Many-Core System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Phase noise improvement and noise modeling of type-I ADPLL with non-linear quantization effects.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Silicon synapse designs for VLSI neuromorphic platform.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Customizing 6LoWPAN networks towards Internet-of-Things based ubiquitous healthcare systems.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Towards energy-efficient HealthCare: An Internet-of-Things architecture using intelligent gateways.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Pervasive health monitoring based on Internet of Things: Two case studies.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Web-Enabled Intelligent Gateways for eHealth Internet-of-Things.
Proceedings of the Internet of Things. User-Centric IoT, 2014

Dark silicon aware power management for manycore systems under dynamic workloads.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

HiWA: A hierarchical Wireless Network-on-Chip architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

NeuroCGRA: A CGRA with support for neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Exploring NoC jitter effect on simulation of spiking neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

TransPar: Transformation based dynamic Parallelism for low power CGRAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Multi-agent Based Architecture for Dynamic VM Consolidation in Cloud Data Centers.
Proceedings of the 40th EUROMICRO Conference on Software Engineering and Advanced Applications, 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Parameterized AES-Based Crypto Processor for FPGAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Energy-efficient concurrent testing approach for many-core systems in the dark silicon age.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Automated formal approach for debugging dividers using dynamic specification.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Online testing of many-core systems in the Dark Silicon era.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

From self-aware building blocks to self-organizing systems with hierarchical agent-based adaptation.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Hierarchical VM Management Architecture for Cloud Data Centers.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

Adjustable contiguity of run-time task allocation in networked many-core systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Positioning Antifragility for Clouds on Public Infrastructures.
Proceedings of the 5th International Conference on Ambient Systems, 2014

Energy-Aware Dynamic VM Consolidation in Cloud Data Centers Using Ant Colony System.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

2013
A Hybrid Low Power Biopatch for Body Surface Potential Measurement.
IEEE J. Biomed. Health Informatics, 2013

ELL-i: An inexpensive platform for fixed things.
Scalable Comput. Pract. Exp., 2013

Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip.
Microprocess. Microsystems, 2013

Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes.
Microprocess. Microsystems, 2013

Optimal placement of vertical connections in 3D Network-on-Chip.
J. Syst. Archit., 2013

A development and verification framework for the SegBus platform.
J. Syst. Archit., 2013

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip.
J. Syst. Archit., 2013

A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.
J. Syst. Archit., 2013

Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels.
J. Comput. Syst. Sci., 2013

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.
J. Comput. Syst. Sci., 2013

Cluster Based Networks-on-Chip: An Efficient and Fault-Tolerant Architecture using Network Interface Assisted Routing.
Int. J. Adapt. Resilient Auton. Syst., 2013

RFID antenna humidity sensor co-design for USN applications.
IEICE Electron. Express, 2013

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip.
J. Electron. Test., 2013

Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

PDNOC: An Efficient Partially Diagonal Network-on-Chip Design.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

Hierarchical Supporting Structure for Dynamic Organization in Many-core Computing Systems.
Proceedings of the PECCS 2013, 2013

Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access.
Proceedings of the Parallel Computing Technologies - 12th International Conference, 2013

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

From traditional VLSI education to embedded electronics.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

FPGA implementation of AES-based crypto processor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Optimized multicore architectures for data parallel fast Fourier transform.
Proceedings of the Computer Systems and Technologies, 2013

MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration.
Proceedings of the Computer Systems and Technologies, 2013

Private configuration environments (PCE) for efficient reconfiguration, in CGRAs.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Modeling of Energy Dissipation in RLC Current-Mode Signaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Bio-Patch Design and Implementation Based on a Low-Power System-on-Chip and Paper-Based Inkjet Printing Technology.
IEEE Trans. Inf. Technol. Biomed., 2012

Memory-Efficient On-Chip Network With Adaptive Interfaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.
J. Low Power Electron., 2012

Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems.
Int. J. Embed. Real Time Commun. Syst., 2012

Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability.
Int. J. Embed. Real Time Commun. Syst., 2012

Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study.
Int. J. Adapt. Resilient Auton. Syst., 2012

Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses.
IET Comput. Digit. Tech., 2012

Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip.
IET Circuits Devices Syst., 2012

Green wideband RFID tag antenna for supply chain applications.
IEICE Electron. Express, 2012

Exploration of heuristic scheduling algorithms for 3D multicore processors.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.
Proceedings of the PECCS 2012, 2012

An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Dual Congestion Awareness scheme in On-Chip Networks.
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

A high-efficiency low-cost heterogeneous 3D network-on-chip design.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication.
Proceedings of the International SoC Design Conference, 2012

Adaptive synchronization and integration region optimization for energy detection IR-UWB receivers.
Proceedings of the IEEE International Conference on Ultra-Wideband, 2012

Vertical and horizontal integration towards collective adaptive system: a visionary approach.
Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012

Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

HLS-DoNoC: High-level simulator for dynamically organizational NoCs.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Towards Reuse-Based Development for the On-chip Distributed SoC Architecture.
Proceedings of the 36th Annual IEEE Computer Software and Applications Conference Workshops, 2012

A Cluster-Based Core Protection Technique for Networks-on-Chip.
Proceedings of the 36th Annual IEEE Computer Software and Applications Conference, 2012

ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Low-Power and Flexible Energy Detection IR-UWB Receiver for RFID and Wireless Sensor Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A study of 3D Network-on-Chip design for data parallel H.264 coding.
Microprocess. Microsystems, 2011

Service based communication for MPSoC platform-SegBus.
Microprocess. Microsystems, 2011

A generic adaptive path-based routing method for MPSoCs.
J. Syst. Archit., 2011

Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.
IET Circuits Devices Syst., 2011

Agent-based on-chip network using efficient selection method.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Efficient congestion-aware selection method for on-chip networks.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

High-performance on-chip network platform for memory-on-processor architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors.
Proceedings of the PECCS 2011, 2011

Insight into the Requirements of Self-aware, Adaptive and Reliable Embedded Sub-systems of Satellite Spacecraft.
Proceedings of the PECCS 2011, 2011

Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.
Proceedings of the PECCS 2011, 2011

A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

PVS-NoC: Partial Virtual Channel Sharing NoC Architecture.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Explorations of optimal core and cache placements for Chip Multiprocessor.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.
Proceedings of the NOCS 2011, 2011

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.
Proceedings of the NOCS 2011, 2011

Power-Efficient Inter-Layer Communication Architectures for 3D NoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A Minimal Average Accessing Time Scheduler for Multicore Processors.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Study of Hierarchical N-Body Methods for Network-on-Chip Architectures.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Evaluating Sustainability, Environmental Assessment and Toxic Emissions during Manufacturing Process of RFID Based Systems.
Proceedings of the IEEE Ninth International Conference on Dependable, 2011

Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach.
Proceedings of the 35th Annual IEEE International Computer Software and Applications Conference, 2011

Optimal memory controller placement for chip multiprocessor.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Cluster-based topologies for 3D stacked architectures.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Change Function of 2D/3D Network-on-Chip.
Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip.
ACM Trans. Embed. Comput. Syst., 2010

Interconnection alternatives for hierarchical monitoring communication in parallel SoCs.
Microprocess. Microsystems, 2010

Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification.
Int. J. Embed. Real Time Commun. Syst., 2010

An automated control code generation approach for the SegBus platform.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A Low-Latency and Memory-Efficient On-chip Network.
Proceedings of the NOCS 2010, 2010

BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Performance Analysis of 3D NoCs Partitioning Methods.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

High-Performance TSV Architecture for 3-D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Input-Output Selection Based Router for Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Power-aware NoC router using central forecasting-based dynamic virtual channel allocation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A Performance Estimation Technique for the SegBus Distributed Architecture.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Resource-aware task allocation and scheduling for segbus platform.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Power- and performance-aware IP mapping for NoC-based MPSoC platforms.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

An Emulation Solution for the SegBus Platform.
Proceedings of the 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, 2010

Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers.
Proceedings of the 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, 2010

Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Partitioning methods for unicast/multicast traffic in 3D NoC architecture.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits.
Proceedings of the Design, Automation and Test in Europe, 2010

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Operating System Processor Scheduler Design for Future Chip Multiprocessor.
Proceedings of the ARCS '10, 2010

CMIT - A novel cluster-based topology for 3D stacked architectures.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A DSL for the SegBus platform.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Intelligent electrode design for long-term ECG monitoring at home: Prototype design using FPAA and FPGA.
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009

Explorations of Honeycomb Topologies for Network-on-Chip.
Proceedings of the NPC 2009, 2009

Scalability of network-on-chip communication architecture for 3-D meshes.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

System-level exploration of run-time clusterization for energy-efficient on-chip communication.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.
Proceedings of the Design, Automation and Test in Europe, 2009

An ASIC Solution for Intelligent Electrodes and Active-Cable used in a Wearable ECG Monitoring System.
Proceedings of the BIODEVICES 2009, 2009

Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication.
Proceedings of the Architecture of Computing Systems, 2009

Adaptive Sub-Threshold Test Circuit.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

3-D memory organization and performance analysis for multi-processor network-on-chip architecture.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Computational Scheme Based on Random Boolean Networks.
Trans. Comp. Sys. Biology, 2008

Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Application development flow for on-chip distributed architectures.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

An ASIC-design-based configurable SOC architecture for networked media.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

A Model-Based Design Process for the SegBus Distributed Architecture.
Proceedings of the 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March, 2008

On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
An efficient passive RFID system for ubiquitous identification and sensing using impulse UWB radio.
Elektrotech. Informationstechnik, 2007

Delay-Balanced Smart Repeaters for On-Chip Global Signaling.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Baseband design for passive semi-UWB wireless sensor and identification systems.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Early selection of system implementation choice among SoC, SoP and 3-D Integration.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Power Management and Clock Generator for a Novel Passive UWB Tag.
Proceedings of the International Symposium on System-on-Chip, 2007

A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Towards a Design Methodology for Multiprocessor Platforms.
Proceedings of the 31st Annual International Computer Software and Applications Conference, 2007

A computational model based on Random Boolean Networks.
Proceedings of the 2nd International ICST Conference on Bio-Inspired Models of Network, 2007

Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
Analytical model for crosstalk and intersymbol interference in point-to-point buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On-Chip Distributed Architectures.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Investigation of Timing Jitter in NAND and NOR Gates Induced by Power-Supply Noise.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Modeling delay and noise in arbitrarily coupled RC trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Robustness enhancement through chip-package co-design for high-speed electronics.
Microelectron. J., 2005

Guest Editors' Introduction: Multiprocessor Systems-on-Chips.
Computer, 2005

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.
Proceedings of the Integrated Circuit and System Design, 2005

The SoC-Mobinet Model in System-on-Chip Education.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

A Modified Cascaded Sigma-Delta Modulator with Improved Linearity.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Case study of interconnect analysis for standing wave oscillator design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A concurrent multi-band LNA for multi-standard radios.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Computing attractors in dynamic networks.
Proceedings of the AC 2005, 2005

2004
Efficient library characterization for high-level power estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Interconnect intellectual property for Network-on-Chip (NoC).
J. Syst. Archit., 2004

Special issue on networks on chip.
J. Syst. Archit., 2004

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.
Integr., 2004

A circuit-switched network architecture for network-on-chip.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers.
Proceedings of the Integrated Circuit and System Design, 2004

Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Crosstalk immune interconnect driver design.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

SoC-Mobinet, R&D and education in system-on-chip design.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Global routing for multicast-supporting TDM network-on-chip.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Performance analysis of sampling switches in voltage and frequency domains using Volterra series.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

RF robustness enhancement through statistical analysis of chip package co-design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Maximizing throughput over parallel wire structures in the deep submicrometer regime.
IEEE Trans. Very Large Scale Integr. Syst., 2003

System level interconnect design for network-on-chip using interconnect IPs.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

A guaranteed-throughput switch for network-on-chip.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A global wire planning scheme for Network-on-Chip.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Will Networks on Chip Close the Productivity Gap?
Proceedings of the Networks on Chip, 2003

2002
Energy Efficient Signaling in Deep-submicron Technology.
VLSI Design, 2002

On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Interconnection of autonomous error-tolerant cells.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On dynamic delay and repeater insertion.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Optimising bandwidth over deep sub-micron interconnect.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Interconnect peak current reduction for wavelet array processor using self-timed signaling.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A structure of cascading multi-bit modulators without dynamic element matching or digital correction.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of clock jitter effects in wideband sigma-delta modulators for rf-applications.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A multi-bit sigma-delta modulator for wideband applications.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

HIPED: a tool for high-level power estimation of digital signal processing algorithms.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Repeater Insertion To Minimise Delay In Coupled Interconnects.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

SOCWARE: A New Swedish Design Cluster for System-on-Chip.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Digital Hardware Organization Course for SoC Program.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Energy Efficient Signaling in Deep Submicron CMOS Technology.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

High-speed serial communication with error correction using 0.25 um CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Sigma delta modulators using semi-uniform quantizers.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Energy efficient signaling in DSM CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Fast low-power characterization of arithmetic units in DSM CMOS.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Efficient and accurate modeling of power supply noise on distributed on-chip power networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Combating digital noise in high speed ULSI circuits using binary BCH encoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

New metrics for architectural level power performance evaluation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A fifth-order comb decimation filter for multi-standard transceiver applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Comparison of OFDM and WPM for fourth generation broadband WLAN.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Effective power and ground distribution scheme for deep submicron high speed VLSI circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Globally asynchronous locally synchronous architecture for large high-performance ASICs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of a super-pipelined Viterbi decoder.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A model for predicting sampler RF bandwidth and conversion loss.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Combinatorial architectural level power optimization for a class of orthogonal transforms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process.
Proceedings of the VLSI: Systems on a Chip, 1999

Phase noise in sampling and its importance to wideband multicarrier base station receivers.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
Implementation aspects for noncoherent tracking based on a time-discrete delay-locked loop.
Proceedings of the 9th IEEE International Symposium on Personal, 1998

1997
System oriented VLSI curriculum at KTH.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1996
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
VLSI implementation of DS-CDMA receiver using asynchronous design techniques.
Proceedings of the 6th IEEE International Symposium on Personal, 1995

Noise Suppression System Integration Using an Analog Allpass Filter Bank.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
The Walkstation transceiver design.
Proceedings of 44th IEEE Vehicular Technology Conference: Creating Tomorrow's Mobile Systems, 1994

Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs.
Proceedings of the Field-Programmable Logic, 1994

DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.
Proceedings of the Field-Programmable Logic, 1994

Hardware/software partitioning and minimizing memory interface traffic.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
DSP system integration and prototyping with FPGAS.
J. VLSI Signal Process., 1993

1992
Technologies and Utilization fo Field Programmable Gate Arrays.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1991
Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991


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