Sandeep Saini

Orcid: 0000-0002-8906-8639

According to our database1, Sandeep Saini authored at least 27 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Real-time attention-based embedded LSTM for dynamic sign language recognition on edge devices.
J. Real Time Image Process., April, 2024

2023
Hybrid deep learning model-based human action recognition in indoor environment.
Robotica, December, 2023

Enhancing Privacy-Preserving Brain Tumor Detection in Medical Cyber-Physical Systems through Deep Learning Algorithms.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Asana Uplift: Elevating Yoga Practice with Deep Learning and Raspberry Pi 4.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Human Action Recognition Using ConvBiLSTM-GRU In Indoor Environment.
Proceedings of the IEEE Global Conference on Artificial Intelligence and Internet of Things, 2023

2022
Hardware-Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment.
IEEE Consumer Electron. Mag., 2022

Stock values predictions using deep learning based hybrid models.
CAAI Trans. Intell. Technol., 2022

2021
Hardware Software Co-design framework for Data Encryption in Image Processing Systems for the Internet of Things Environmen.
CoRR, 2021

A novel model based on Sequential Adaptive Memory for English-Hindi Translation.
Cogn. Comput. Syst., 2021

Dynamic Two Hand Gesture Recognition using CNN-LSTM based networks.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

FPGA based Implementation of Binarized Neural Network for Sign Language Application.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Stock Market Predictions Using FastRNN-Based Model.
Proceedings of the Seventh International Conference on Mathematics and Computing, 2021

2020
Cognitive architecture for natural language comprehension.
Cogn. Comput. Syst., 2020

Hardware Software Co-Simulation of an AES-128 based Data Encryption in Image Processing Systems for the Internet of Things Environment.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Bilingual Sentiment Analysis for a Code-mixed Punjabi English Social Media Text.
Proceedings of the 5th International Conference on Computing, Communication and Security, 2020

2019
Image processing-based intelligent robotic system for assistance of agricultural crops.
Int. J. Soc. Humanist. Comput., 2019

2017
A hybrid approach to emotion recognition system using multi-discriminant analysis & k-nearest neighbour.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

Securing qr codes by rsa on fpga.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

2016
A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Bayesian learner based language learnability analysis of Hindi.
Proceedings of the 2016 International Conference on Advances in Computing, 2016

FPGA based hardware implementation of automatic vehicle license plate detection system.
Proceedings of the 2016 International Conference on Advances in Computing, 2016

2015
Relative clause based text simplification for improved English to Hindi translation.
Proceedings of the 2015 International Conference on Advances in Computing, 2015

2014
A novel design of compact reversible SG gate and its applications.
Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

2013
Design of low power and high speed multiplexer based Thermometer to Gray encoder.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

2010
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
J. Low Power Electron., 2010

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Implementation of low power FFT structure using a method based on conditionally coded blocks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


  Loading...