Anurag Mahajan

According to our database, Anurag Mahajan authored at least 13 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An error-efficient Gaussian filter for image processing by using the expanded operand decomposition logarithm multiplication.

Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan

J. Ambient Intell. Humaniz. Comput., January, 2024

2023

Automatic Liver Cancer Detection Using Deep Convolution Neural Network.

Kiran Malhari Napte, Anurag Mahajan, Shabana Urooj

IEEE Access, 2023

Expert System for Real Time Arm Movement Recognition Based on Surface EMG Signal.

Shripad Bhatlawande, Swati Shilaskar, Mahesh Kinge, Anurag Mahajan

Proceedings of the Computational Intelligence in Data Science, 2023

2021

Polycystic Ovarian Syndrome Detection by Using Two-Stage Image Denoising.

Shruti Bhargava Choubey, Abhishek Choubey, Durgesh Nandan, Anurag Mahajan

Traitement du Signal, 2021

Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications.

Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena

Turkish J. Electr. Eng. Comput. Sci., 2021

2019

Analytical modelling and experimental study of machining of smart materials using submerged abrasive waterjet micromachining process.

Anurag Mahajan, Sagil James

Int. J. Manuf. Res., 2019

Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems.

Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2017

An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition.

Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan

Integr., 2017

2013

Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT.

Basant K. Mohanty, Anurag Mahajan

J. Low Power Electron., 2013

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer.

Basant K. Mohanty, Anurag Mahajan

IET Circuits Devices Syst., 2013

2012

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT.

Basant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2010

Implementation of low power FFT structure using a method based on conditionally coded blocks.

Sandeep Saini, Anurag Mahajan, Srinivas B. Mandalika

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic.

Anurag Mahajan, Basant K. Mohanty

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010