Sandhya Koteshwara
Orcid: 0000-0003-3182-219X
  According to our database1,
  Sandhya Koteshwara
  authored at least 20 papers
  between 2016 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
  2025
    Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
    
  
  2024
Position Paper: From Confidential Computing to Zero Trust, Come Along for the (Bumpy?) Ride.
    
  
    Proceedings of the 13th International Workshop on Hardware and Architectural Support for Security and Privacy, 2024
    
  
    Proceedings of the 24th IEEE International Symposium on Cluster, 2024
    
  
S2TAR: Shared Secure Trusted Accelerators with Reconfiguration for Machine Learning in the Cloud.
    
  
    Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024
    
  
  2023
    Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
    
  
  2021
    Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
    
  
  2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
    
  
    J. Hardw. Syst. Secur., 2020
    
  
    Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020
    
  
Performance Optimization of Lattice Post-Quantum Cryptographic Algorithms on Many-Core Processors.
    
  
    Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
    
  
  2019
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 2019
    
  
ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch.
    
  
    Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
    
  
  2018
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design.
    
  
    IEEE Trans. Inf. Forensics Secur., 2018
    
  
Incremental-Precision Based Feature Computation and Multi-Level Classification for Low-Energy Internet-of-Things.
    
  
    IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
    
  
Low-Energy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and Multi-Level Classification.
    
  
    Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
    
  
  2017
Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications.
    
  
    IEEE Des. Test, 2017
    
  
Hierarchical functional obfuscation of integratec circuits using a mode-based approach.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
    
  
FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
    
  
    Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
    
  
Performance comparison of AES-GCM-SIV and AES-GCM algorithms for authenticated encryption on FPGA platforms.
    
  
    Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
    
  
  2016
    Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016