Chris H. Kim

According to our database1, Chris H. Kim authored at least 147 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment.
IEEE Trans. Biomed. Circuits Syst., 2019

A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer.
IEEE J. Solid State Circuits, 2019

An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm.
IEEE J. Solid State Circuits, 2019

A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Real-time HR Estimation from wrist PPG using Binary LSTMs.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design.
IEEE Trans. Inf. Forensics Secur., 2018

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer.
IEEE J. Solid State Circuits, 2018

A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A 0.0094mm<sup>2</sup>/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

Effect of aging on linear and nonlinear MUX PUFs by statistical modeling.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Reliable PUF-Based Local Authentication With Self-Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit.
IEEE J. Solid State Circuits, 2017

A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.
IEEE J. Solid State Circuits, 2017

R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices.
CoRR, 2017

A Non-volatile Near-Memory Read Mapping Accelerator.
CoRR, 2017

Predicting hard and soft-responses and identifying stable challenges of MUX PUFs using ANNs.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An entropy test for determining whether a MUX PUF is linear or nonlinear.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Hierarchical functional obfuscation of integratec circuits using a mode-based approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Advanced spintronic memory and logic for non-volatile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements.
Proceedings of the 54th Annual Design Automation Conference, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

A DRAM based physical unclonable function capable of generating >10<sup>32</sup> Challenge Response Pairs per 1Kbit array for secure chip authentication.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Functional encryption of integrated circuits by key-based hybrid obfuscation.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 0.0054-mm<sup>2</sup> Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis.
ACM J. Emerg. Technol. Comput. Syst., 2016

CoMET: Composite-Input Magnetoelectric-based Logic Technology.
CoRR, 2016

19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Mode-based Obfuscation using Control-Flow Modifications.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016

Estimating delay differences of arbiter PUFs using silicon data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor.
Proc. IEEE, 2015

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.
Proceedings of the Symposium on VLSI Circuits, 2015

A 8-14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design.
IEEE Micro, 2014

A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications.
IEEE J. Solid State Circuits, 2014

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter.
IEEE J. Solid State Circuits, 2014

Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Improving STT-MRAM density through multibit error correction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

True Random Number Generator circuits based on single- and multi-phase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme.
IEEE J. Solid State Circuits, 2013

A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.
IEEE J. Solid State Circuits, 2013

A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of V<sub>MIN</sub> Degradation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation.
IEEE J. Solid State Circuits, 2012

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.
IEEE J. Solid State Circuits, 2012

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor.
IEEE J. Solid State Circuits, 2012

Process and Reliability Sensors for Nanoscale CMOS.
IEEE Des. Test Comput., 2012

A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme.
Proceedings of the Symposium on VLSI Circuits, 2012

Design of ring oscillator structures for measuring isolated NBTI and PBTI.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2011

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization.
IEEE J. Solid State Circuits, 2011

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.
IEEE J. Solid State Circuits, 2011

Guest editors' introduction: Nanoscale Memories Pose Unique Challenges.
IEEE Des. Test Comput., 2011

A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On-chip reliability monitors for measuring circuit degradation.
Microelectron. Reliab., 2010

An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB.
IEEE J. Solid State Circuits, 2010

Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise.
IEEE J. Solid State Circuits, 2010

Variation aware performance analysis of gain cell embedded DRAMs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Logic-compatible embedded DRAM design for memory intensive low power systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V<sub>min</sub> Lowering Techniques and Deep Sleep Mode.
IEEE J. Solid State Circuits, 2009

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit.
IEEE J. Solid State Circuits, 2009

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Circuit techniques for enhancing the clock data compensation effect under resonant supply noise.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Adaptive techniques for overcoming performance degradation due to aging in digital circuits.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Body Bias Voltage Computations for Process and Temperature Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits.
IEEE J. Solid State Circuits, 2008

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.
IEEE J. Solid State Circuits, 2008

Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Enhancing <i>beneficial jitter</i> using phase-shifted clock distribution.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A multi-story power delivery technique for 3D integrated circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Circuit techniques for ultra-low power subthreshold SRAMs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Modeling Subthreshold Leakage Current in General Transistor Networks.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Sleep transistor sizing and control for resonant supply noise damping.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Modeling and estimating leakage current in series-parallel CMOS networks.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

NBTI-Aware Synthesis of Digital Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
Proceedings of the 44th Design Automation Conference, 2007

An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro, 2006

Impact of NBTI on SRAM Read Stability and Design for Reliability.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Modeling and analysis of leakage induced damping effect in low voltage LSIs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An analytical model for negative bias temperature instability.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
Proceedings of the 43rd Design Automation Conference, 2006

Width Quantization Aware FinFET Circuit Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Multi-story power delivery for supply noise reduction and low voltage operation.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Leakage in nano-scale technologies: mechanisms, impact and design considerations.
Proceedings of the 41th Design Automation Conference, 2004

2003
Gate leakage reduction for scaled devices using transistor stacking.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A forward body-biased low-leakage SRAM cache: device and architecture considerations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Dynamic VTH Scaling Scheme for Active Leakage Power Reduction.
Proceedings of the 2002 Design, 2002


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