Martin Ohmacht

Orcid: 0000-0001-5423-0512

According to our database1, Martin Ohmacht authored at least 24 papers between 1995 and 2023.

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Bibliography

2023
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2018

2015
Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q.
IEEE Trans. Computers, 2015

Active Memory Cube: A processing-in-memory architecture for exascale systems.
IBM J. Res. Dev., 2015

2013
IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory.
IBM J. Res. Dev., 2013

2012
The IBM Blue Gene/Q Compute Chip.
IEEE Micro, 2012

Evaluation of blue Gene/Q hardware support for transactional memories.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2007
The Blue Gene/L Supercomputer: A Hardware and Software Story.
Int. J. Parallel Program., 2007

2005
Verification strategy for the Blue Gene/L chip.
IBM J. Res. Dev., 2005

Blue Gene/L compute chip: Memory and Ethernet subsystem.
IBM J. Res. Dev., 2005

Blue Gene/L compute chip: Control, test, and bring-up infrastructure.
IBM J. Res. Dev., 2005

Blue Gene/L advanced diagnostics environment.
IBM J. Res. Dev., 2005

Overview of the Blue Gene/L system architecture.
IBM J. Res. Dev., 2005

Blue Gene/L compute chip: Synthesis, timing, and physical design.
IBM J. Res. Dev., 2005


2004
The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

2002
Kopplung von Scheduling- und Allokationsphase für ILP-Prozessoren mit heterogenem Registersatz.
PhD thesis, 2002

An overview of the BlueGene/L Supercomputer.
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Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002


2000
A 1.3-GOPS parallel DSP for high-performance image-processing applications.
IEEE J. Solid State Circuits, 2000

1999
HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999

Cellular Multiprocessor Arrays with Adaptive Resource Utilization.
Proceedings of the Parallel Computation, 1999

1998
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications.
Proceedings of the 35th Conference on Design Automation, 1998

1995
Architecture and C++-programming environment of a highly parallel image signal processor.
Microprocess. Microprogramming, 1995


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