Saravanan Padmanaban

According to our database1, Saravanan Padmanaban authored at least 11 papers between 2001 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2006
Implicit grading of multiple path delay faults.
ACM Trans. Design Autom. Electr. Syst., 2006

2005
Efficient identification of (critical) testable path delay faults using decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
A Critical Path Selection Method for Delay Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Adaptive Path Delay Fault Diagnosis Methodology.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Low power ATPG for path delay faults.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.
Proceedings of the 2004 Design, 2004

2003
An implicit path-delay fault diagnosis methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Exact path delay fault coverage with fundamental ZBDD operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Non-Enumerative Path Delay Fault Diagnosis .
Proceedings of the 2003 Design, 2003

2002
Exact Grading of Multiple Path Delay Faults.
Proceedings of the 2002 Design, 2002

2001
Exact path delay grading with fundamental BDD operations.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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