Spyros Tragoudas

According to our database1, Spyros Tragoudas authored at least 232 papers between 1990 and 2020.

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2020
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays.
IEEE Trans. VLSI Syst., 2020

2019
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations.
IEEE Trans. VLSI Syst., 2019

Low Power Artificial Neural Network Architecture.
CoRR, 2019

2018
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions.
IEEE Trans. on Circuits and Systems, 2018

An Aging Resilient Neural Network Architecture.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors.
Proceedings of the IEEE International Test Conference, 2018

Test set identification for improved delay defect coverage in the presence of statistical delays.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Threshold Voltage Extraction Using Static NBTI Aging.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

A Method to Model Statistical Path Delays for Accurate Defect Coverage.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Delay Analysis for Current Mode Threshold Logic Gate Designs.
IEEE Trans. VLSI Syst., 2017

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

More Efficient Testing of Metal-Oxide Memristor-Based Memory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges.
Journal of Circuits, Systems, and Computers, 2017

Aging-aware critical paths for process related validation in the presence of NBTI.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

METS: A multiple event transient simulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Reducing power, area, and delay of threshold logic gates considering non-integer weights.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Efficient computation of the sensitization probability of a critical path considering process variations and path correlation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Diagnosis with transition faults on embedded segments.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Efficient Critical Path Selection Under a Probabilistic Delay Model.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A new method to identify threshold logic functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2016

ATPG for Delay Defects in Current Mode Threshold Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Compressive image sensor technique with sparse measurement matrix.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

An Enhanced Analytical Electrical Masking Model for Multiple Event Transients.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Efficient selection of critical paths for delay defects in the presence of process variations.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Identification of delay defects on embedded paths using one current sensor.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

A Highly Robust Double Node Upset Tolerant latch.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Fast march tests for defects in resistive memory.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Unreachable code identification for improved line coverage.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Towards Trojan circuit detection with maximum state transition exploration.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Non-enumerative correlation-aware path selection.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A BIST approach for counterfeit circuit detection based on NBTI degradation.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Error Correction Encoding for Tightly Coupled On-Chip Buses.
IEEE Trans. VLSI Syst., 2014

Adapting an Implicit Path Delay Grading Method for Parallel Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

On-Chip Codeword Generation to Cope With Crosstalk.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Nanopipelined threshold network synthesis.
JETC, 2014

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms.
JETC, 2014

Scalable Offline Searches in DNA Sequences.
JETC, 2014

Aging-aware critical paths in deep submicron.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Adaptive compressive sensing for low power wireless sensors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A novel parallel adaptation of an implicit path delay grading method.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

ATPG for transition faults of pipelined threshold logic circuits.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Diagnosis of segment delay defects with current sensing.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Enhanced Secure Architecture for Joint Action Test Group Systems.
IEEE Trans. VLSI Syst., 2013

A Probabilistic Approach to Diagnose SETs in Sequential Circuits.
J. Electronic Testing, 2013

Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A method to determine the sensitization probability of a non-robustly testable path.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Performance validation through implicit removal of infeasible paths of the behavioral description.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Error detection encoding for multi-threshold capture mechanism.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Low power and high speed current-mode memristor-based TLGs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic.
IEEE Trans. Computers, 2012

An efficient heuristic to identify threshold logic functions.
JETC, 2012

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission.
Ad Hoc Networks, 2012

Delay Analysis for an N-Input Current Mode Threshold Logic Gate.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Non-enumerative generation of statistical path delays for ATPG.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A scalable threshold logic synthesis method using ZBDDs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Transient pulse propagation using the Weibull distribution function.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Accurate calculation of SET propagation probability for hardening.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Improved diagnosis using enhanced fault dominance.
Integr., 2011

An analytical method for estimating SET propagation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Occurrence probability analysis of a path at the architectural level.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Multi-level secure JTAG architecture.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error correction encoding for multi-threshold capture mechanism.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Probabilistic Approach to Diagnose SETs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Scalable Method for Identifying DNA Substrings Using Functions.
Proceedings of the ISCA 3rd International Conference on Bioinformatics and Computational Biology, 2011

2010
Identification of Delay Measurable PDFs Using Linear Dependency Relationships.
IEEE Trans. VLSI Syst., 2010

Techniques to Prioritize Paths for Diagnosis.
IEEE Trans. VLSI Syst., 2010

A Data Capturing Method for Buses on Chip.
IEEE Trans. on Circuits and Systems, 2010

Scan Shift Power Reduction by Gating Internal Nodes.
J. Low Power Electronics, 2010

A novel probabilistic SET propagation method.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

On-line detection of random voltage perturbations in buses with multiple-threshold receivers.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Probabilistic methods for the impact of an SET in combinational logic.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Scalable identification of threshold logic functions.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Gating internal nodes to reduce power during scan shift.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Scalable codeword generation for coupled buses.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
Graph Theory and Algorithms.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Identification of Critical Executable Paths at the Architectural Level.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Low-power multi-core ATPG to target concurrency.
Integr., 2008

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.
J. Electronic Testing, 2008

A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model.
Proceedings of the 2008 IEEE International Test Conference, 2008

A High-Performance Bus Architecture for Strongly Coupled Interconnects.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Novel Test Generation Methodology for Adaptive Diagnosis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Propagation of Transients Along Sensitizable Paths.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Prioritization of Paths for Diagnosis.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Speedups in embedded systems with a high-performance coprocessor datapath.
ACM Trans. Design Autom. Electr. Syst., 2007

High-Quality Transition Fault ATPG for Small Delay Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Managing the power resources of sensor networks with performance considerations.
Comput. Commun., 2007

Accelerating Diagnosis via Dominance Relations between Sets of Faults.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Glitch Control with Dynamic Receiver Threshold Adjustment.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Enhanced Identification of Strong Robustly Testable Paths.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Implicit grading of multiple path delay faults.
ACM Trans. Design Autom. Electr. Syst., 2006

Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A high-performance data path for synthesizing DSP kernels.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

InTeRail: A Test Architecture for Core-Based SOCs.
IEEE Trans. Computers, 2006

Interconnect Testing for Networks on Chips.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Exact At-speed Delay Fault Grading in Sequential Circuits.
Proceedings of the 2006 IEEE International Test Conference, 2006

Minimizing FPGA Reconfiguration Data at Logic Level.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An Improved Method for Identifying Linear Dependencies in Path Delay Faults.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Evaluation of Collapsing Methods for Fault Diagnosis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Sub-faults identification for collapsing in diagnosis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Implicit Critical PDF Test Generation with Maximal Test Efficiency.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Function-based compact test pattern generation for path delay faults.
IEEE Trans. VLSI Syst., 2005

On-chip embedding mechanisms for large sets of vectors for delay test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Efficient identification of (critical) testable path delay faults using decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Rewiring for watermarking digital circuit netlists.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Low Power Test Generation for Path Delay Faults.
J. Low Power Electronics, 2005

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels.
Journal of Circuits, Systems, and Computers, 2005

A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Minimum Cut Based Re-Synthesis Approach.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Design and Evaluation of a Security Scheme for Sensor Networks.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Functions for Quality Transition Fault Tests.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reduced Test Application Time Based on Reachability Analysis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Towards finding path delay fault tests with high test efficiency using ZBDDs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Quality Transition Fault Tests Suitable for Small Delay Defects.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Test set enhancement for quality transition faults using function-based methods.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Low power test generation for path delay faults using stability functions.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A security protocol for sensor networks.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
Proceedings of the 2005 Design, 2005

2004
Implicit deductive fault simulation for complex delay fault models.
IEEE Trans. VLSI Syst., 2004

A unified framework for generating all propagation functions for logic errors and events.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A Novel Data-Path for Accelerating DSP Kernels.
Proceedings of the Computer Systems: Architectures, 2004

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
Proceedings of the Integrated Circuit and System Design, 2004

Identification of Gates for Covering all Critical Paths.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Compact ATPG for Concurrent SOC Testing.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On-line Testing Field Programmable Analog Array Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A Critical Path Selection Method for Delay Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Adaptive Path Delay Fault Diagnosis Methodology.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Rewiring for Watermarking Digital Circuits.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A high performance data-path to accelerate DSP kernels.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Security enhancement through multiple path transmission in ad hoc networks.
Proceedings of IEEE International Conference on Communications, 2004

Low power ATPG for path delay faults.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
Proceedings of the Field Programmable Logic and Application, 2004

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.
Proceedings of the 2004 Design, 2004

2003
Path delay fault testing using test points.
ACM Trans. Design Autom. Electr. Syst., 2003

An implicit path-delay fault diagnosis methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Exact path delay fault coverage with fundamental ZBDD operations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.
J. Electronic Testing, 2003

Generation of Hazard Identification Functions.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Non-Enumerative Path Delay Fault Diagnosis .
Proceedings of the 2003 Design, 2003

2002
ATPG tools for delay faults at the functional level.
ACM Trans. Design Autom. Electr. Syst., 2002

A new built-in TPG method for circuits with random patternresistant faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

On the nonenumerative path delay fault simulation problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Disjoint Paths with Length Constraints.
I. J. Comput. Appl., 2002

Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
J. Electronic Testing, 2002

An efficient algorithm for finding a path subject to two additive constraints.
Comput. Commun., 2002

Exact Grading of Multiple Path Delay Faults.
Proceedings of the 2002 Design, 2002

2001
The most reliable data-path transmission.
IEEE Trans. Reliability, 2001

Von Neumann hybrid cellular automata for generating deterministic test sequences.
ACM Trans. Design Autom. Electr. Syst., 2001

Computational analysis of counter-based schemes for VLSI test pattern generation.
Discret. Appl. Math., 2001

Exact path delay grading with fundamental BDD operations.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

ATPG for Path Delay Faults without Path Enumeration.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Color Counting and its Application to Path Delay Fault Coverage.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Test-set partitioning for multi-weighted random LFSRs.
Integr., 2000

Routing with energy considerations in mobile ad-hoc networks.
Proceedings of the 2000 IEEE Wireless Communications and Networking Conference, 2000

Power dissipation component of a management protocol for ad-hoc networks.
Proceedings of the 2000 IEEE Wireless Communications and Networking Conference, 2000

Methods for on-chip embedding of path delay test vectors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
CAD Tools for BIST/DFT and Delay Faults.
Proceedings of the VLSI Handbook., 1999

Board-level partitioning for partial scan using fuzzy logic.
IEEE Trans. Fuzzy Systems, 1999

A fast nonenumerative automatic test pattern generator for pathdelay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

On the design of optimal counter-based schemes for test set embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Transmissions in a network with capacities and delays.
Networks, 1999

Maximum weighted independent sets on transitive graphs and applications1.
Integr., 1999

Accurate path delay fault coverage is feasible.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Embedded cores using built-in mechanisms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Functional ATPG for Delay Faults.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Testing for Path Delay Faults Using Test Points.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Timing-Driven Circuit Implementation.
VLSI Design, 1998

Clustering Network Modules with Different Implementations for Delay Minimization.
VLSI Design, 1998

A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On-Chip Test Embedding for Multi-Weighted Random LFSRs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Implementing and clustering modules with complex delays.
Integr., 1997

Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Maximum independent sets on transitive graphs and their applications in testing and CAD.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Cellular automata for generating deterministic test sequences.
Proceedings of the European Design and Test Conference, 1997

1996
A fast algorithm for minimizing FPGA combinational and sequential modules.
ACM Trans. Design Autom. Electr. Syst., 1996

Min-Cut Partitioning on Underlying Tree and Graph Structures.
IEEE Trans. Computers, 1996

On the Use of Counters for Reproducing Deterministic Test Sets.
IEEE Trans. Computers, 1996

Retiming-Based Partial Scan.
IEEE Trans. Computers, 1996

Improved Approximations for the Minimum-Cut Ratio and the Flux.
Mathematical Systems Theory, 1996

Computing Disjoint Path with Lenght Constraints.
Proceedings of the Graph-Theoretic Concepts in Computer Science, 1996

Generating deterministic unordered test patterns with counters.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

ATPD: An Automatic Test Pattern Generator for Path Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

FPGA Module Minimization.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A multiseed counter TPG with performance guarantee.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Deterministic Test Pattern Reproduction by a Counter.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Pseudo-exhaustive built-in TPG for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Fast Approximation Algorithms for Multicommodity Flow Problems.
J. Comput. Syst. Sci., 1995

Bipartitioning into Overlapping Sets.
Int. J. Found. Comput. Sci., 1995

Avoiding linear dependencies in LFSR test pattern generators.
J. Electronic Testing, 1995

On the Computation of Fast Data Transmissions in Networks with Capacities and Delays.
Proceedings of the Algorithms and Data Structures, 4th International Workshop, 1995

Quickest paths: parallelization and dynamization .
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

Uniform area timing-driven circuit implementation.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
A method for pseudo-exhaustive test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

The Problem of Partitioning with Duplications and its Applications.
International Journal on Artificial Intelligence Tools, 1994

A design for testability technique for test pattern generation with LFSRs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

High Performance Over-the-Cell Routing.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

An improved algorithm for the generalized min-cut partitioning problem.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Retiming algorithms with application to VLSI testability.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Mathematical model for routability analysis of FPGAs.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.
IEEE Trans. VLSI Syst., 1993

River routing and density minimization for channels with interchangeable terminals.
Integr., 1993

Searching a Pseudo 3-Sided Solid Orthoconvex Grid.
Int. J. Found. Comput. Sci., 1993

Pseudoexhaustive BIST for Sequential Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Minmax-cut graph partitioning problems.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Partial Scan with Retiming.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Approximate solutions for Graph and Hypergraph Partitioning.
Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992
Circuit partitioning into small sets.
Microprocess. Microsystems, 1992

Searching a Solid Pseudo 3-Sided Orthoconvex Grid.
Proceedings of the Algorithms and Computation, Third International Symposium, 1992

On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
A comparative study of five language independent programming environments.
J. Syst. Softw., 1991

Circuit partitioning into small sets: a tool to support testing with further applications.
Proceedings of the conference on European design automation, 1991

1990
Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems.
Proceedings of the Graph-Theoretic Concepts in Computer Science, 1990


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