Maria K. Michael
Orcid: 0000-0002-1943-6547
According to our database1,
Maria K. Michael
authored at least 100 papers
between 1999 and 2024.
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Bibliography
2024
A Geometrical Approach to Enhance Security Against Cyber Attacks in Digital Substations.
IEEE Access, 2024
2023
A Machine Learning Approach for Detecting GPS Location Spoofing Attacks in Autonomous Vehicles.
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023
Robust Cooperative Sparse Representation Solutions for Detecting and Mitigating Spoofing Attacks in Autonomous Vehicles.
Proceedings of the 31st Mediterranean Conference on Control and Automatio, 2023
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2023
Protection and Communication Model of Intelligent Electronic Devices to Investigate Security Threats.
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2023
Modelling and Analysing Security Threats Targeting Protective Relay Operations in Digital Substations.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023
Reputation-based User Vehicle Assignment in Intelligent and Connected Vehicle Platoons.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023
2022
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
SafeDrones: Real-Time Reliability Evaluation of UAVs Using Executable Digital Dependable Identities.
Proceedings of the Model-Based Safety and Assessment - 8th International Symposium, 2022
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Two-dimensional Dataset Reduction in Data-Driven Fault Detection for IoT-based Cyber Physical Systems.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
2021
TrustPH: Trustworthy Platoon Head Selection considering Cognitive Biases to enhance Secure Platooning in Intelligent and Connected Vehicles.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021
A behavioral model to detect data manipulation attacks of synchrophasor measurements.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2021
Light-weight and Robust Network Intrusion Detection for Cyber-attacks in Digital Substations.
Proceedings of the 2021 IEEE PES Innovative Smart Grid Technologies, 2021
Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Guest Editor's Introduction: Special Section on Reliability-Aware Design and Analysis Methods for Digital Systems: From Gate to System Level.
IEEE Trans. Emerg. Top. Comput., 2020
Classifying network abnormalities into faults and attacks in IoT-based cyber physical systems using machine learning.
Microprocess. Microsystems, 2020
Proceedings of the 2020 IEEE International Conference on Smart Internet of Things, 2020
Cost-Effective Time-Redundancy Based Optimal Task Allocation for the Edge-Hub-Cloud Systems.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2020
Proceedings of the 11th International Conference on Information, 2020
Special Session: Physics- Informed Neural Networks for Securing Water Distribution Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Dataset Reduction Framework For Intelligent Fault Detection In IoT-based Cyber-Physical Systems Using Machine Learning Techniques.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020
2019
Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Differentiating Attacks and Faults in Energy Aware Smart Home System using Supervised Machine Learning.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019
2018
Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology.
IEEE Trans. Emerg. Top. Comput., 2018
J. Electron. Test., 2018
Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering.
J. Electron. Test., 2018
2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors.
IEEE Trans. Computers, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2015
IEEE Trans. Computers, 2015
IEEE Des. Test, 2015
Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
In-field vulnerability analysis of hardware-accelerated computer vision applications.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Tackling the complexity of exact path delay fault grading for path intensive circuits.
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
Microprocess. Microsystems, 2014
Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Exploration of system availability during software-based self-testing in many-core systems under test latency constraints.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Test set embedding into accumulator-generated sequences targeting hard-to-detect faults.
Proceedings of the 8th International Design and Test Symposium, 2013
On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems.
Proceedings of the 8th International Design and Test Symposium, 2013
DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Educ., 2012
J. Electron. Test., 2012
Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors.
Proceedings of the 2012 IEEE International Test Conference, 2012
2011
EURASIP J. Embed. Syst., 2011
Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration.
Proceedings of the 16th European Test Symposium, 2011
2010
Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques.
IEEE Trans. Computers, 2010
Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback.
EURASIP J. Embed. Syst., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
2009
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.
J. Electron. Test., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
Proceedings of the Applications of Evolutionary Computing, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
A unified framework for generating all propagation functions for logic errors and events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999