Mahilchi Milir Vaseekar Kumar

According to our database, Mahilchi Milir Vaseekar Kumar authored at least 8 papers between 2004 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

High-Quality Transition Fault ATPG for Small Delay Defects.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Exact At-speed Delay Fault Grading in Sequential Circuits.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Low Power Test Generation for Path Delay Faults.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas

J. Low Power Electron., 2005

Quality Transition Fault Tests Suitable for Small Delay Defects.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Low power test generation for path delay faults using stability functions.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Implicit and Exact Path Delay Fault Grading in Sequential Circuits.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

Proceedings of the 2005 Design, 2005

2004

Low power ATPG for path delay faults.

Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004