Sasindu Wijeratne
Orcid: 0000-0002-5538-2988Affiliations:
- University of Southern California, CA, USA
- University of Moratuwa, Sri Lanka (former)
According to our database1,
Sasindu Wijeratne
authored at least 21 papers
between 2017 and 2025.
Collaborative distances:
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Bibliography
2025
AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs.
CoRR, July, 2025
2024
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images.
CoRR, 2024
Predictive Performance of Photonic SRAM-Based in-Memory Computing for Tensor Decomposition.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2024
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU $\mathcal{X}_{(d)}$.
Proceedings of the 58th Asilomar Conference on Signals, 2024
2023
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2022
Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
Proceedings of the 11th International Conference on Data Science, 2022
2021
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks.
CoRR, 2021
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2021
2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
2018
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017