Satoshi Yamane

According to our database, Satoshi Yamane authored at least 93 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Extrinsicaly Rewarded Soft Q Imitation Learning with Discriminator.

Ryoma Furuyama, Daiki Kuyoshi, Satoshi Yamane

CoRR, 2024

Combined Constraint on Behavior Cloning and Discriminator in Offline Reinforcement Learning.

Shunya Kidera, Kosuke Shintani, Toi Tsuneda, Satoshi Yamane

IEEE Access, 2024

2023

Enhanced Full Attention Generative Adversarial Networks.

Kaixu Chen, Satoshi Yamane

IEICE Trans. Inf. Syst., May, 2023

Staged Depthwise Correlation and Feature Fusion for Siamese Object Tracking.

Dianbo Ma, Jianqiang Xiao, Ziyan Gao, Satoshi Yamane

Proceedings of the International Joint Conference on Neural Networks, 2023

2022

Single and Ensemble CNN Models with Out-Category Penalty for Image Classification.

Yuta Suzuki, Daiki Kuyoshi, Satoshi Yamane

Int. J. Netw. Comput., 2022

M-DenseUNet: Multi Dense Encoder Connected UNet for Biomedical Image Segmentation.

Tongdan Jin, Kaixu Chen, Satoshi Yamane, Yoshihiro Kuroda

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

Regularization to Suppress Mode Collapse in GANs Using Image Similarity.

Kuniyasu Imade, Taro Kiriyama, Satoshi Yamane

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021

Optimizing 3D Convolution Kernels on Stereo Matching for Resource Efficient Computations.

Jianqiang Xiao, Dianbo Ma, Satoshi Yamane

Sensors, 2021

An Image Classification Model that Learns Image Features and Numerical Information.

Yuta Suzuki, Toshiki Hatano, Toi Tsuneda, Daiki Kuyoshi, Satoshi Yamane

Int. J. Netw. Comput., 2021

GBDT Modeling of Deep Reinforcement Learning Agents Using Distillation.

Toshiki Hatano, Toi Tsuneda, Yuta Suzuki, Kuniyasu Imade, Kazuki Shesimo, Satoshi Yamane

Proceedings of the IEEE International Conference on Mechatronics, 2021

GANs with Suppressed Mode Collapse Using Intrinsic Rewards.

Toi Tsuneda, Taro Kiriyama, Kousuke Shintani, Satoshi Yamane

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Single and Ensemble CNN Models with Out-Category Penalty in Cifar 10.

Yuta Suzuki, Daiki Kuyoshi, Satoshi Yamane

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Loss Function of GAN to Make a Clear Judgment.

Kuniyasu Imade, Toi Tsuneda, Satoshi Yamane, Kousuke Shintani, Taro Kiriyama

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

SAFPN: Self Adapted Feature Pyramid Networks for Object Detection.

Zhiying Zhou, Jianqiang Xiao, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

CBAM-Unet++: easier to find the target with the attention module "CBAM".

Zhengxuan Zhao, Kaixu Chen, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Population Based Training for Text Classification Using Convolutional Neural Network.

Xie Zhang, Mo Li, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Shuffle in 3D: A Lightweight Architecture for Stereo Matching.

Jianqiang Xiao, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Enhanced EVA with Threshold Limit of Similarity.

Toi Tsuneda, Kuniyasu Imade, Kousuke Shintani, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

A Classifier for Reducing Numerical Errors using Ensemble Method.

Yuta Suzuki, Toi Tsuneda, Daiki Kuyoshi, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Proposal of Ephemeral Value Adjustment with Dimensionality Reduction in Deep Reinforcement Learning.

Daiki Kuyoshi, Yuta Suzuki, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Reduction of Timer Interrupts for Embedded Assembly Programs Based on Reduction of Interrupt Handler Executions.

Taro Kiriyama, Yajun Wu, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

A study of DQN using VisionTransformer as an image extractor.

Toshiki Hatano, Toi Tsuneda, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Enhanced Conditions Based Deep Convolutional Generative Adversarial Networks.

Kaixu Chen, Zhengxuan Zhao, Satoshi Yamane

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

Accelerating Model Validation by Reconstructing Image Sets Using GAN.

Toshiki Hatano, Taro Kiriyama, Toi Tsuneda, Satoshi Yamane

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

2020

Model Checking of Real-Time Properties for Embedded Assembly Program Using Real-Time Temporal Logic RTCTL and Its Application to Real Microcontroller Software.

Yajun Wu, Satoshi Yamane

IEICE Trans. Inf. Syst., 2020

Practical Evaluation of Online Heterogeneous Machine Learning.

Kazuki Seshimo, Akira Ota, Daichi Nishio, Satoshi Yamane

IEICE Trans. Inf. Syst., 2020

Q-learning in Continuous Action Space by Extending EVA.

Toi Tsuneda, Daiki Kuyoshi, Satoshi Yamane

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

An Image Classification Model that Learns MNIST Image Features and Numerical Information.

Yuta Suzuki, Toshiki Hatano, Toi Tsuneda, Satoshi Yamane

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Efficient Exploration by Decision Making Considering Curiosity and Episodic Memory in Deep Reinforcement Learning.

Daiki Kuyoshi, Kuniyasu Imade, Satoshi Yamane

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Image Classification with Additional Non-decision Labels using Self-supervised learning and GAN.

Toshiki Hatano, Toi Tsuneda, Yuta Suzuki, Kousuke Shintani, Satoshi Yamane

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Comparative Experiment of SPIN and SMT in Model Checking of Embedded Assembly Program.

Satoshi Yamane, Kosuke Uemura

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Software Model Checking for Real-time Properties of Embedded Assembly Programs Based on Lazy Abstraction and Refinement.

Yajun Wu, Hiromu Kamide, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Proposal of Quantized Tree-LSTM and Its Experimental Evaluation.

Kazuki Takamura, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Transfer Learning Model for Image Segmentation by Integrating U-Net ++ and SE Block.

Yuta Suzuki, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Discriminator Soft Actor Critic without Extrinsic Rewards.

Daichi Nishio, Toi Tsuneda, Daiki Kuyoshi, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Text Classification using Convolutional Neural Network by Genetic Algorithms.

Mo Li, Xie Zhang, Satoshi Yamane, Ang Yang Lin

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Rainbow with Episodic Memory in Deep Reinforcement Learning.

Daiki Kuyoshi, Toi Tsuneda, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Angle Estimation Network Using Polar Transformation for Object Classification.

Nishiki Katayama, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Boosting Binary Neural Networks for FPGA.

Toshiki Hatano, Satoshi Yamane

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

2019

Gap Detection Using Convolutional Neural Network and Adaptive Control in Robotic Plasma Welding.

Satoshi Yamane, Kouki Matsuo

Int. J. Autom. Technol., 2019

Machine translation considering context information using Encoder-Decoder model.

Tetsuto Takano, Satoshi Yamane

CoRR, 2019

Improving Minimal Gated Unit for Sequential Data.

Kazuki Takamura, Satoshi Yamane

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Online Heterogeneous Mixture Learning for Big Data.

Kazuki Seshimo, Akira Ota, Daichi Nishio, Satoshi Yamane

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Generalize IoT Device's Client Application with Virtual Machine.

Hiroki Kawakami, Satoshi Yamane

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

SMT-Based Bounded Model Checking of Embedded Assembly Program with Interruptions.

Kousuke Uemura, Satoshi Yamane

Proceedings of the 2019 IEEE Intl Conf on Dependable, 2019

Random Projection in Neural Episodic Control.

Daichi Nishio, Satoshi Yamane

Proceedings of The 11th Asian Conference on Machine Learning, 2019

2018

Machine Translation Considering Context Informaiton Using Encoder-Decoder Model.

Satoshi Yamane, Tetsuto Takano

Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

Model Checking of Embedded Systems Using RTCTL While Generating Timed Kripke Structure.

Yajun Wu, Satoshi Yamane

Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

Faster Deep Q-Learning Using Neural Episodic Control.

Daichi Nishio, Satoshi Yamane

Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

Model Check of Real-time Property of Embedded Assembly Program Using CEGAR.

Hiromu Kamide, Kosuke Uemura, Satoshi Yamane

Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

2017

Model Checking of Embedded Assembly Program Based on Simulation.

Satoshi Yamane, Ryosuke Konoshita, Tomonori Kato

IEICE Trans. Inf. Syst., 2017

Deductively verifying embedded software in the era of artificial intelligence = machine learning + software science.

Satoshi Yamane

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

Recognition of rotated images by angle estimation using feature map with CNN.

Nishiki Katayama, Satoshi Yamane

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2016

LogChamber: Inferring Source Code Locations Corresponding to Mobile Applications Run-time Logs.

Yuki Ono, Kouhei Sakurai, Satoshi Yamane

J. Inf. Process., 2016

A Case Study of Formal Approach to Dynamically Reconfigurable Systems by Using Dynamic Linear Hybrid Automata.

Ryo Yanase, Tatsunori Sakai, Makoto Sakai, Satoshi Yamane

Proceedings of the Formal Methods and Software Engineering, 2016

Detecting bank conflict of GPU programs using symbolic execution.

Koki Hamaya, Satoshi Yamane

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2015

Formal verification of dynamically reconfigurable systems.

Ryo Yanase, Tatsunori Sakai, Makoto Sakai, Satoshi Yamane

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Distributed CFG-based symbolic execution for assembly programs.

Takumi Adachi, Satoshi Yamane, Kohei Sakurai

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

Development of probabilistic timed CEGAR.

Satoshi Yamane, Takaya Shimizu

Proceedings of the 2nd International Conference on Systems and Informatics, 2014

Model generation by the exhaustive search for embedded assembly programs and application to model checking.

Ryosuke Konoshita, Kouhei Sakurai, Satoshi Yamane

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Development of SMT-Based Bounded Model Checker for embedded assembly program.

Jumpei Kobashi, Satoshi Yamane, Atsushi Takeshita

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2013

Development of Model Checker of Dynamic Linear Hybrid Automata.

Ryo Yanase, Tatsunori Sakai, Makoto Sakai, Satoshi Yamane

Proceedings of the 37th Annual IEEE Computer Software and Applications Conference, 2013

2008

Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications.

Satoshi Yamane

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Theory and Practice of Probabilistic Timed Game for Embedded Systems.

Satoshi Yamane

Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

2005

Symbolic Reachability Analysis of Probabilistic Linear Hybrid Automata.

Yosuke Mutsuda, Takaaki Kato, Satoshi Yamane

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Deductive Probabilistic Verification Methods of Safety, Liveness and Nonzenoness for Distributed Real-Time Systems.

Satoshi Yamane

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Specification and Verification Techniques of Embedded Systems Using Probabilistic Linear Hybrid Automata.

Yosuke Mutsuda, Takaaki Kato, Satoshi Yamane

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Automata-Theoretic Performance Analysis Method of Soft Real-Time Systems.

Satoshi Yamane

Proceedings of the Embedded and Ubiquitous Computing - EUC 2005 Workshops, 2005

Timed Weak Simulation Verification and Its Application to Stepwise Refinement of Real-Time Software.

Satoshi Yamane

Proceedings of the Embedded and Ubiquitous Computing, 2005

2004

Development and evaluation of symbolic model checker based on approximation for real-time systems.

Satoshi Yamane, Kazuhiro Nakamura

Syst. Comput. Jpn., 2004

Deductive Verification of Probabilistic Real-Time Systems.

Satoshi Yamane

Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Deductive Probabilistic Verification Methods for Embedded and Ubiquitous Computing.

Satoshi Yamane, Takashi Kanatani

Proceedings of the Embedded and Ubiquitous Computing, 2004

2003

Formal Probabilistic Refinement Verification of Embedded Real-Time Systems.

Satoshi Yamane

Proceedings of the 1st IEEE Workshop on Software Technologies for Future Embedded Systems, 2003

Deductive Schedulability Verification Methodology of Real-Time Software using both Refinement Verification and Hybrid Automata.

Satoshi Yamane

Proceedings of the 27th International Computer Software and Applications Conference (COMPSAC 2003): Design and Assessment of Trustworthy Software-Based Systems, 2003

Probabilistic Timed Simulation Verification and Its Application to Stepwise Refinement of Real-Time Systems.

Satoshi Yamane

Proceedings of the Advances in Computing Science, 2003

1999

Real-Time Symbolic Model Checking for Hard Real-Time Systems.

Y. Tachi, Satoshi Yamane

Proceedings of the 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 1999

1998

Automatic Effective Verification Method for Distributed and Concurrent Systems Using Timed Language Inclusion.

Satoshi Yamane

Scalable Comput. Pract. Exp., 1998

Hierarchical Design Method for Real-Time Distributed Systems.

Satoshi Yamane

Proceedings of the 5th International Workshop on Real-Time Computing Systems and Applications (RTCSA '98), 1998

Traffic Signal Control Using Multi-layered Fuzzy Control.

Satoshi Yamane, Kazuhiro Okada, Kenji Shinoda, Kenji Oshima

Proceedings of the Rough Sets and Current Trends in Computing, 1998

Sensing of Arc Length and Wire Extension Using Neural Network in Robotic Welding.

Kazuhiko Eguchi, Satoshi Yamane, Hideo Sugi, Kenji Oshima

Proceedings of the Rough Sets and Current Trends in Computing, 1998

An Application of Genetic Algorithms to Floorplanning of VLSI.

Kazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima

Proceedings of the Rough Sets and Current Trends in Computing, 1998

A Practical Hierarchical Design by Timed Simulation Relations for Real-Time Systems.

Satoshi Yamane

Proceedings of the Applied Formal Methods, 1998

Formal Verification of Real-Time Software by Symbolic Model-Checker.

Kazuhiro Nakamura, Satoshi Yamane

Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997

A method for the specification and verification of distributed systems by a timed automaton.

Satoshi Yamane

Syst. Comput. Jpn., 1997

Symbolic Model-Checking Method Based on Approximations and Binary Decision Diagrams for Real-Time Systems.

Satoshi Yamane, Kazuhiro Nakamura

Proceedings of the Theoretical Aspects of Computer Software, Third International Symposium, 1997

Formal Specification and Verification Method of Concurrent and Distributed Systems by Restricted Timed Automata.

Satoshi Yamane

Proceedings of the Transformation-Based Reactive Systems Development, 1997

1996

Proposal of hybrid verification method in asynchronous real-time software including timing constraints specification.

Satoshi Yamane

Syst. Comput. Jpn., 1996

Object-oriented method for real-time systems based on timed automaton.

Satoshi Yamane

Proceedings of WORDS'96. The Second Workshop on Object-Oriented Real-Time Dependable Systems, 1996

The verification technique of real-time systems using probabilities.

Satoshi Yamane

Proceedings of the Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30, 1996

The Symbolic Model-Checking for Real-Time Systems.

Satoshi Yamane

Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

1995

Verification system for real-time specification based on extended real-time logic.

Satoshi Yamane

Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications, October 25, 1995

Real-Time Object-Oriented Method.

Satoshi Yamane

Proceedings of the 1995 International Conference on Object Oriented Information Systems, 1995

Formal Timing Verification Techniques for Distributed System .

Satoshi Yamane

Proceedings of the 5th IEEE Workshop on Future Trends of Distributed Computing Systems (FTDCS 1995), 1995