Sehyeon Chung

According to our database, Sehyeon Chung authored at least 14 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Utilization of standard cells with hybrid-threshold-voltage for timing and power optimization.

Sehyeon Chung, Taewhan Kim

Integr., 2026

Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries.

Hyunbae Seo, Sehyeon Chung, Taewhan Kim

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes.

Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques.

Yeongyeong Shin, Sehyeon Chung, Taewhan Kim

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

Synthesis of Standard Cells of Minimum Delay.

Sehyeon Chung, Hyunbae Seo, Taewhan Kim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing.

Jaehoon Ahn, Sehyeon Chung, Taewhan Kim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery.

Sehyeon Chung, Hyun-chul Hwang, Byung-Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes.

Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes.

Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility.

Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

ECO routing based on network flow method.

Sehyeon Chung, Taewhan Kim

Integr., 2022

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.

Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis.

Sehyeon Chung, Jooyeon Jeong, Taewhan Kim

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021

Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops.

Jaejoon Yoon, Sehyeon Chung, Taewhan Kim

Proceedings of the 18th International SoC Design Conference, 2021