Taewhan Kim

According to our database1, Taewhan Kim authored at least 165 papers between 1991 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization.
IEEE Trans. VLSI Syst., 2019

Hybrid asynchronous circuit generation amenable to conventional EDA flow.
Integration, 2019

SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
Synthesis and exploration of clock spines.
IET Computers & Digital Techniques, 2018

Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Clock buffer and flip-flop co-optimization for reducing peak current noise.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and algorithm for clock gating and flip-flop co-optimization.
Proceedings of the International Conference on Computer-Aided Design, 2018

Structure optimizations of neuromorphic computing architectures for deep neural network.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Loosely coupled multi-bit flip-flop allocation for power reduction.
Integration, 2017

Boundary optimization of buffered clock trees for low power.
Integration, 2017

Clock buffer polarity assignment under useful skew constraints.
Integration, 2017

Switch cell optimization of power-gated modern system-on-chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Algorithm for synthesis and exploration of clock spines.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes.
Integration, 2016

Grey-level context-driven histogram equalisation.
IET Image Processing, 2016

Synthesizing Asynchronous Circuits toward Practical Use.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Allocation of multi-bit flip-flops in logic synthesis for power optimization.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Synthesis of TSV Fault-Tolerant 3-D Clock Trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Context-driven hybrid image inpainting.
IET Image Processing, 2015

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Synthesis for Power-Aware Clock Spines.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Integrated Resource Allocation and Binding in Clock Mesh Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2014

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis.
Integration, 2014

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs.
Integration, 2014

Post-silicon tunable clock buffer allocation based on fast chip yield computation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Fast algorithm of low power image reformation for OLED display.
Proceedings of the Sixth International Conference on Digital Image Processing, 2014

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Statistical Viability Analysis for Detecting False Paths Under Delay Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

High-level TSV resource sharing and optimization for TSV based 3D IC designs.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Tutorial: Methodology for designing reliable clock networks.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Power Saving by Task-Level Dynamic Voltage Scaling.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint.
ACM Trans. Design Autom. Electr. Syst., 2012

Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Design Methodologies for Reliable Clock Networks.
JCSE, 2012

Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling.
Comput. J., 2012

Die matching algorithm for enhancing parametric yield of 3D ICs.
Proceedings of the International SoC Design Conference, 2012

Algorithm for synthesizing design context-aware fast carry-skip adders.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits.
IEEE Trans. VLSI Syst., 2011

Scheduling and Resource Binding Algorithm Considering Timing Variation.
IEEE Trans. VLSI Syst., 2011

Clock Tree synthesis for TSV-based 3D IC designs.
ACM Trans. Design Autom. Electr. Syst., 2011

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead.
Proceedings of the International SoC Design Conference, 2011

Clock design techniques considering circuit reliability.
Proceedings of the International SoC Design Conference, 2011

A fine-grained timing driven synthesis of arithmetic circuits.
Proceedings of the International SoC Design Conference, 2011

WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing.
Proceedings of the 48th Design Automation Conference, 2011

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results.
JCSE, 2010

Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC.
Comput. J., 2010

Clock buffer polarity assignment considering the effect of delay variations.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew.
Proceedings of the International Green Computing Conference 2010, 2010

Clock tree synthesis with pre-bond testability for 3D stacked IC designs.
Proceedings of the 47th Design Automation Conference, 2010

Technique for controlling power-mode transition noise in distributed sleep transistor network.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Clock tree embedding for 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Thermal sensor allocation and placement for reconfigurable systems.
ACM Trans. Design Autom. Electr. Syst., 2009

Thermal-Aware High-Level Synthesis Based on Network Flow Method.
Journal of Circuits, Systems, and Computers, 2009

Autonomous temperature control technique in VLSI circuits through logic replication.
IET Computers & Digital Techniques, 2009

Interconnect and communication synthesis for distributed register-file microarchitecture.
IET Computers & Digital Techniques, 2009

Timing variation-aware high-level synthesis considering accurate yield computation.
Proceedings of the 27th International Conference on Computer Design, 2009

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
Proceedings of the 46th Design Automation Conference, 2009

Timing variation-aware task scheduling and binding for MPSoC.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Hotspots Elimination and Temperature Flattening in VLSI Circuits.
IEEE Trans. VLSI Syst., 2008

Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst., 2008

Power-gating-aware high-level synthesis.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Timing variation-aware high level synthesis: Current results and research challenges.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

DC-DC Converter-Aware Power Management for Low-Power Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Temperature-Aware Compilation for VLIWProcessors.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Address Code Optimization Exploiting Code Scheduling in DSP Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Timing variation-aware high-level synthesis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.
Proceedings of the 44th Design Automation Conference, 2007

2006
Resource Sharing Combined with Layout Effects in High-Level Synthesis.
VLSI Signal Processing, 2006

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications.
VLSI Signal Processing, 2006

Technique for Transition Energy-Aware Dynamic Voltage Assignment.
IEEE Trans. on Circuits and Systems, 2006

Optimal intratask dynamic voltage-scaling technique and its practical extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Memory Access Driven Storage Assignment for Variables in Embedded System Design.
Journal of Circuits, Systems, and Computers, 2006

Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

HW/SW partitioning techniques for multi-mode multi-task embedded applications.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A systematic IP and bus subsystem modeling for platform-based system design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Thermal-aware high-level synthesis based on network flow method.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Optimal voltage allocation techniques for dynamically variable voltage processors.
ACM Trans. Embedded Comput. Syst., 2005

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.
Proceedings of the 42nd Design Automation Conference, 2005

DC-DC converter-aware power management for battery-operated embedded systems.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.
IEEE Trans. VLSI Syst., 2004

Coupling-aware high-level interconnect synthesis [IC layout].
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
IEEE Trans. Computers, 2004

Leakage power minimization for the synthesis of parallel multiplier circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Profile-based optimal intra-task voltage scheduling for hard real-time applications.
Proceedings of the 41th Design Automation Conference, 2004

Memory access scheduling and binding considering energy minimization in multi-bank memory systems.
Proceedings of the 41th Design Automation Conference, 2004

An integrated approach to timing-driven synthesis and placement of arithmetic circuits.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Memory access driven storage assignment for variables in embedded system design.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Resource-constrained low-power bus encoding with crosstalk delay elimination.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. VLSI Syst., 2003

High-level synthesis for low power based on network flow method.
IEEE Trans. VLSI Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. VLSI Syst., 2003

Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst., 2003

Synthesis of arithmetic circuits considering layout effects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Address assignment in DSP code generation - an integrated approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Bus Optimization for Low Power in High-Level Synthesis.
Journal of Circuits, Systems, and Computers, 2003

An efficient inverse multiplier/divider architecture for cryptography systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Optimal voltage allocation techniques for dynamically variable voltage processors.
Proceedings of the 40th Design Automation Conference, 2003

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
Proceedings of the 40th Design Automation Conference, 2003

2002
Synthesis and Optimization of Combinational Interface Circuits.
VLSI Signal Processing, 2002

Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

A Complete Model for Glitch Analysis in Logic Circuits.
Journal of Circuits, Systems, and Computers, 2002

Binding Algorithm for Power Optimization Based on Network Flow Method.
Journal of Circuits, Systems, and Computers, 2002

Memory exploration utilizing scheduling effects in high-level synthesis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Enhanced bus invert encodings for low-power.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Address code optimization using code scheduling for digital signal processors.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An efficient low-power binding algorithm in high-level synthesis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Layout-driven resource sharing in high-level synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Coupling-aware high-level interconnect synthesis for low power.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Layout-aware synthesis of arithmetic circuits.
Proceedings of the 39th Design Automation Conference, 2002

An integrated algorithm for memory allocation and assignment in high-level synthesis.
Proceedings of the 39th Design Automation Conference, 2002

Address assignment combined with scheduling in DSP code generation.
Proceedings of the 39th Design Automation Conference, 2002

2001
G-vector: A New Model for Glitch Analysis in Logic Circuits.
VLSI Signal Processing, 2001

An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.
IEEE Trans. Computers, 2001

An Integrated Data Path Optimization for Low Power Based on Network Flow Method.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An accurate evaluation of routing density for symmetrical FPGAs.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

A Static Estimation Technique of Power Sensitivity in Logic Circuits.
Proceedings of the 38th Design Automation Conference, 2001

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.
Proceedings of ASP-DAC 2001, 2001

2000
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.
VLSI Design, 2000

A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.
Journal of Circuits, Systems, and Computers, 2000

Decomposition of Bus-Invert Coding for Low-Power I/O.
Journal of Circuits, Systems, and Computers, 2000

A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Behavioral-level partitioning for low power design in control-dominated application.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.
Proceedings of the 37th Conference on Design Automation, 2000

A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
Optimal allocation of carry-save-adders in arithmetic optimization.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Register Allocation - A Hierarchical Reduction Approach.
VLSI Signal Processing, 1998

Circuit optimization using carry-save-adder cells.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Arithmetic Optimization Using Carry-Save-Adders.
Proceedings of the 35th Conference on Design Automation, 1998

1996
An integrated algorithm for incremental data path synthesis.
VLSI Signal Processing, 1996

1995
A new approach to the multiport memory allocation problem in data path synthesis.
Integration, 1995

1994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Register allocation for data flow graphs with conditional branches and loops.
Proceedings of the European Design Automation Conference 1993, 1993

Utilization of Multiport Memories in Data Path Synthesis.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1991
A Scheduling Algorithm for Conditional Resource Sharing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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