Seryeong Kim
According to our database1,
Seryeong Kim
authored at least 6 papers
between 2023 and 2025.
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Bibliography
2025
IRIS: A 8.55mJ/frame Spatial Computing SoC for Interactable Rendering and Surface-Aware Modeling with 3D Gaussian Splatting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 51.2 fps Real-Time 3DGS-SLAM Accelerator using Diagonal Feeding with Symmetric Alpha Reuse and Voxel-based 3D Gaussian Cache Management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
An Energy-Efficient CNN/Transformer Hybrid Neural Semantic Segmentation Processor With Chunk-Based Bit Plane Data Compression and Similarity-Based Token-Level Skipping Exploitation.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 3.55 mJ/frame Energy-efficient Mixed-Transformer based Semantic Segmentation Accelerator for Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023