Soyeon Um
Orcid: 0000-0002-8526-2047
According to our database1,
Soyeon Um
authored at least 17 papers
between 2020 and 2024.
Collaborative distances:
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Bibliography
2024
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.
IEEE J. Solid State Circuits, January, 2024
2023
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit.
IEEE J. Solid State Circuits, October, 2023
Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks.
IEEE J. Solid State Circuits, October, 2023
Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 3.8 mW 1.9 m Ω/√Hz Electrical Impedance Tomography Imaging with 28.4 M Ω High Input Impedance and Loading Calibration.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network.
CoRR, 2022
A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
2021
A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection.
IEEE J. Solid State Circuits, 2021
2020
A 9.6 mW/Ch 10 MHz Wide-bandwidth Electrical Impedance Tomography IC with Accurate Phase Compensation for Breast Cancer Detection.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020